Read-Once Planar Circuits

• Read-once planar circuits are computational models where each input appears once and the circuit's graph is planar, ensuring a unique structure that affects complexity.
• They support both Boolean and algebraic operations through models like ROFs, ROABPs, and Pfaffian circuits, enabling efficient evaluation and identity testing.
• Their study drives practical insights into lower bounds, pseudorandom generator design, and quantum as well as scalable nanocomputing implementations.

Read-once planar circuits are a class of computational models in which each input variable is read at most once and the underlying circuit graph is planar—i.e., it admits a drawing in the plane with no edge crossings. These circuits arise in both Boolean and algebraic settings and are closely linked to models such as ordered binary decision diagrams (OBDDs), arithmetic formulas, algebraic branching programs, and constraint satisfaction problems (#CSP). The interplay of the read-once property and planarity introduces distinctive complexity-theoretic features, making these circuits a central object of paper in circuit complexity, algebraic complexity, and quantum computation.

1. Formal Definitions and Core Models

A read-once planar circuit is a directed acyclic graph (DAG) whose leaves are labeled by input variables (each appearing at most once), and internal nodes represent operations (Boolean or arithmetic), with the undirected version of the graph embeddable in the plane without edge crossings (Ramya et al., 14 Sep 2025). For Boolean circuits, the allowed gates are typically from the de Morgan basis, possibly augmented with modular counting gates (MOD[k]) as in ACC⁰ (Anand, 13 Jan 2025). In the arithmetic context, gates compute addition or multiplication over a field (Ramya et al., 14 Sep 2025).

Key related models include:

• Read-once arithmetic formulas (ROFs): Trees with fan-out 1, each leaf labeled by a unique variable; every multilinear polynomial is expressible as a sum of ROFs (Mahajan et al., 2015, Mahajan et al., 2016).
• Read-once oblivious branching programs (ROABPs): Layered models where each variable is restricted to a unique layer, with edges labeled by univariate polynomials (Forbes et al., 2012, Gurjar et al., 2014).
• Pfaffian or holographic circuits: Tensor contraction networks on planar bipartite graphs, used in polynomial-time solvable planar #CSPs (see below) (Margulies et al., 2013, Turner, 2015).
• Quantum read-once branching programs (QOBDDs): Quantum analogues with planarity maintained at the control level, achieving remarkable width reductions via superposition and interference (Ablayev et al., 2011).

2. Structure, Expressiveness, and Hierarchies

Read-once planar circuits enforce substantial structural constraints by restricting each variable to one occurrence and suppressing edge crossings. This leads to several notable consequences:

• Expressiveness: Every multilinear polynomial over a field can be written as a sum of read-once formulas (ROFs); however, for certain families (e.g., symmetric polynomials $S_n^{n-1}$), at least $\lceil n/2 \rceil$ ROFs are required for representation (Mahajan et al., 2015, Mahajan et al., 2016). Hierarchical separations exist: the number of ROF summands strictly governs the computational power, with $\Sigma^k\cdot\mathrm{ROP}$ classes strictly increasing in expressiveness (Mahajan et al., 2015).
• Planar circuits are incomparable with the formula model in terms of size: explicit polynomials exist with formula complexity $n^{1+o(1)}$ but read-once planar circuit complexity $\Omega(n^2)$, and conversely with planar circuit complexity $O(n\log n)$ but formula complexity $\Omega(n^2)$ (Ramya et al., 14 Sep 2025).
• For multi-output computations (e.g., all first-order partial derivatives of a polynomial), planar circuits suffer superlinear lower bounds ($\Omega(n^{4/3})$), refuting Baur-Strassen-style transfer theorems in this model (Ramya et al., 14 Sep 2025).

3. Complexity Lower Bounds and Separations

Lower bounds for read-once planar circuits have seen major advances, particularly for explicit bilinear forms. Key results include:

• Any read-once planar arithmetic circuit computing an explicit bilinear form $y^\top Mx$ (where $M$ is a totally regular matrix) must have size $\Omega(n^2)$ (Ramya et al., 14 Sep 2025). This is tight (matching known upper bounds after planarization).
• For general planar circuits (not read-once), the lower bound for bilinear forms is $\Omega(n\log n)$, achieved via separator arguments using the Lipton-Tarjan theorem (Ramya et al., 14 Sep 2025).
• Sum-of-products models built from read-once polynomials (ROPs) or syntactically multilinear formulas also exhibit exponential lower bounds when computing certain central polynomials, such as the permanent or products of variable-disjoint linear forms (Ramya et al., 2015). For bounded bottom fan-in and number of summands, sizes like $2^{\Omega(n^{1/4})}$ arise.

These bounds demonstrate that planarity and the read-once property interact to sharply limit circuit succinctness, a phenomenon not present in unrestricted or nonplanar models.

4. Algebraic Branching Programs and Polynomial Identity Testing

Read-once oblivious ABPs (ROABPs) form a natural algebraic counterpart for studying identity testing and reconstruction problems under strong structural restrictions. Crucial results include:

• Deterministic black-box identity testing for ROABPs is possible via quasi-polynomial-size hitting sets, with seed length $O(\log^2 S)$ (where S is size), improving to $O(\log^2 S/\log\log S)$ for bounded width. These bounds exceed analogous Boolean PRGs, for which no $o(\log^2 S)$ constructions are known (Forbes et al., 2012).
• The techniques for sums of ROABPs combine low evaluation dimension, basis isolating weight assignments, and low-support rank concentration to achieve quasi-polynomial time deterministic identity tests even for constant summands (Gurjar et al., 2014).
• Several circuit classes, including set-multilinear ABPs, non-commutative ABPs, and semi-diagonal depth-4 circuits, can be black-box reduced to ROABPs for PIT and reconstruction (Forbes et al., 2012).

This algebraic identity testing paradigm underlies lower bound proofs and derandomization efforts in complexity theory.

5. Planarity, Pfaffian Circuits, and Solvable #CSPs

Planar read-once circuits are central to the dichotomy theory for #CSP complexity:

• Pfaffian circuits are tensor networks on planar bipartite graphs where each gate (through carefully chosen change-of-basis matrices) can be written as a subPfaffian of a skew-symmetric matrix (Margulies et al., 2013). Their value is computed in polynomial time via the Pfaffian circuit evaluation theorem: $$\langle \beta\,sPf^*(\tilde\Theta) |\, \alpha\,sPf(\Xi) \rangle = \alpha\beta\,Pf(\tilde\Theta + \Xi)$$.
• Algebraic modeling with polynomial systems (often analyzed using Gröbner bases) enables characterizing which constraint signatures and gates are Pfaffian and hence admit tractable circuit evaluation.
• Decomposition and bridge gadgets allow extension to heterogeneous change-of-basis scenarios, providing a means to represent more complex constraints and simulate nonplanar features. However, simulating staple nonplanar elements such as SWAP gates is only feasible in extremely restricted ways (e.g., a single SWAP gate via basis change and orthogonality), with the inability to absorb multiple SWAP gates (Turner, 2015).

Thus, planarity serves as both an organizing principle for tractability and a barrier to expressiveness.

6. Pseudorandomness, Branching Programs, and Circuit Testing

Read-once planar circuits naturally interface with the theory of pseudorandom generators (PRGs) and branching programs:

• For read-once, constant-depth circuits (including those over the de Morgan basis and in ACC⁰), tailored PRGs achieve seed length $\tilde{O}(\log^{D+1} n)$, leveraging Fourier analytic growth bounds permitted by the read-once structure (Chen et al., 2015). In many cases, the structural properties associated with planarity can further simplify pseudorandom restriction arguments.
• Expander random walks fool two-layered, read-once ACC⁰ circuits composed of MOD[k] gates up to total variation error $O(\lambda)$, where $\lambda$ is the expander's second largest eigenvalue (Anand, 13 Jan 2025). However, explicit threshold circuits in TC⁰ are able to distinguish expander-walk distributions from uniform inputs, demarcating the limitations of such PRGs.
• New combinatorial complexity measures—including the spread of subfunctions and covering/partition numbers—enable new or simpler lower bound proofs for read-once branching programs and their nondeterministic and read-k extensions (Li et al., 2023).

Read-once planarity contributes both technical tractability and vulnerability to exponential lower bounds, as established by complexity measures and pseudorandomness results.

7. Quantum and Physical Realizations

Specializations of read-once planar circuits appear in quantum computation and physical hardware paradigms:

• Quantum read-once branching programs (QOBDDs) exploit superposition and interference via quantum fingerprinting, enabling logarithmic-width constructions for Boolean functions with linear polynomial presentations, versus classical counterparts requiring exponential width (Ablayev et al., 2011). Closure under polynomial projections shows broad applicability of such quantum circuits.
• Planar Clifford circuits (for instance, read-once and constant-depth circuits for measurement-based quantum computation) admit efficient classical simulation in time $O(n^{\omega/2})$ ($n^{1.19}$ for current matrix multiplication exponents), exploiting low treewidth and planarity (Gosset et al., 2020).
• In Field-coupled Nanocomputing (FCN), the physical engineering of read-once planar layouts (for example, via scalable gap-based placement and routing algorithms) enables large-scale, reliable nanocomputing circuits free from signal degradation caused by wire crossings (Hien et al., 11 Apr 2025).
• In topological quantum coding, planar fault-tolerant circuits for non-Clifford gates are constructed by projecting spacetime path integrals onto two-dimensional chips, ensuring locality and planarity (Bauer et al., 8 May 2025).

These advances underscore the relevance of read-once planarity beyond conventional computational models, informing both theoretical complexity and physical design.

8. Open Problems and Directions

Ongoing challenges and avenues for further paper in read-once planar circuits include:

• Constructing explicit constant-degree polynomials requiring superlinear planar circuit size, strengthening known lower bounds (Ramya et al., 14 Sep 2025).
• Extending lower bound and derandomization techniques to finite fields and noncommutative settings.
• Refining gap-based and decomposition techniques in physical designs to balance area, runtime, and reliability (Hien et al., 11 Apr 2025).
• Exploring the limits of classical simulation for quantum architectures with read-once planarity (Gosset et al., 2020).
• Incorporating advanced complexity measures in the analysis of generalized read-k planar branching programs (Li et al., 2023).

The synthesis of algebraic, combinatorial, geometric, and physical constraints positions read-once planar circuits as a focal point for both complexity separation results and practical scalable computation.