Multi-Output Planar Circuits: Theory & Practice

Updated 21 September 2025

Multi-output planar circuits are circuit architectures defined by planar, non-crossing layouts that produce multiple outputs and are used in diverse fields like photonics and quantum computing.
Theoretical studies provide enumeration formulas, complexity lower bounds, and simulation methods that help optimize circuit synthesis and analyze tradeoffs between functionality and layout constraints.
Practical implementation strategies include photonic routing, memristor arrays, and superconducting quantum circuits, which demonstrate enhanced reliability and scalability in advanced systems.

Multi-output planar circuits are circuit architectures wherein multiple outputs are simultaneously realized within a planar (non-crossing) topology. Such designs appear across electrical networks, photonics, arithmetic and Boolean circuits, quantum circuit implementations, and emerging nanocomputing architectures. Theoretical foundations, enumeration, simulation, and lower bound results for multi-output planar circuits occupy critical positions in circuit complexity theory, combinatorics, and applied systems.

1. Definitions and Structural Models

A multi-output planar circuit is defined by the property that its underlying graph can be embedded in the plane without edge crossings and its output set comprises more than one designated gate or port. In the context of arithmetic circuits, this often means simultaneously computing multiple polynomials such as the rows of a linear transformation $y^T M x$ for a totally regular matrix $M$ . In planar electrical networks, multi-output refers to multiple boundary or measurement points, such as the $n$ boundary vertices in a circular planar graph (Alman et al., 2013). Planar circuits are further classified by attributes including read-once property and formula versus general circuit architecture.

The planarity condition is nontrivial since it restricts circuit topology: certain layouts or wiring patterns (such as wire crossings or shared subtrees in formulas) are disallowed or must be realized via specialized gadgets. In some models (e.g., planar algebraic branching programs, quantum circuit graphs, or nanocomputing cell architectures) planarity affects connectivity, circuit depth, and enumerative properties.

2. Combinatorial and Topological Characterization

Circular planar electrical networks are structured by a poset $\mathrm{EP}_n$ whose elements are equivalence classes of networks up to response matrix equivalence (Alman et al., 2013). This poset admits two dual characterizations:

Combinatorial: Classes of circular planar graphs are organized under edge deletions/contractions; [H] $<$ [G] if H is obtainable from G by legal operations.
Topological: Each graph $G$ induces a cell $\Omega(G)$ in the response matrix space; poset order is given by $\Omega(H) \subset \overline{\Omega(G)}$ .

The grading of $\mathrm{EP}_n$ by number of edges in critical representatives provides an intrinsic notion of circuit complexity—the "rank" or minimal number of components in a topologically robust multi-output planar design. This facilitates systematic design navigation, optimization, and analysis of tradeoffs between complexity and function in multi-output settings.

In fault-tolerant quantum circuits, topological path integral methods and ZX tensor networks are leveraged: projections of three-dimensional color codes along specific axes yield planar circuits implementing multi-output non-Clifford gates with nearest-neighbor interactions (Bauer et al., 8 May 2025).

3. Enumerative Analysis and Algorithmic Construction

Explicit enumeration and construction of multi-output planar circuits is central for understanding available design space and its complexity. For circular planar networks, the principal counting result is a recurrence for the number $X_n$ of full wiring diagrams:

$X_n = 2(n-1)X_{n-1} + \sum_{j=2}^{n-2} (j-1) X_j X_{n-j}$

and a generating function relation:

$[t^{n-1}] X(t)^n = n \cdot (2n-3)!!$

with asymptotic density $X_n/(2n-1)!! \to e^{-1/2}$ as $n \to \infty$ (Alman et al., 2013).

Algorithmic construction of circuits—whether photonic manifolds (Chiles et al., 2018), memristive arrays (1705.00244), or logical circuits via non-linear programming (Dimopoulos et al., 2021)—exploits expansion, refinement, and decomposition techniques. In memristor networks, exponential decay of nonlocal coupling as a function of Hamming distance constrains the spread of interactions, simplifying multi-output analysis.

In quantum circuit simulation, exploitation of planar graph treewidth $O(\sqrt{n})$ enables subcubic classical simulation of multi-output planar Clifford circuits via matrix multiplication and tensor contraction algorithms ( $O(n^{\omega/2})$ runtime) (Gosset et al., 2020).

4. Complexity Lower Bounds and Separations

Recent advances have established strong complexity-theoretic lower bounds for multi-output planar circuits (Ramya et al., 14 Sep 2025):

Any planar arithmetic circuit computing an explicit linear transformation $y^T M x$ ( $M$ totally regular) requires size $\Omega(n^{4/3})$ .
Multi-output formulas—a tree-like planar circuit structure with simultaneous outputs—require size $\Omega(n^2 / \log n)$ .

Proofs utilize planar separator lemmas and rank arguments: separator sizes restrict the number of vertex-disjoint paths from inputs to outputs, while ranks of bilinear forms enforce minimal circuit resource requirements. These results are strictly stronger than lower bounds for single-output planar circuits ( $\Omega(n \log n)$ ) and establish fine separations among circuit classes; for read-once planar circuits, the bound increases to $\Omega(n^2)$ for bilinear forms.

Notably, these bounds demonstrate the breakdown of the Baur–Strassen theorem in the planar multi-output setting: whereas in general circuits all first-order partial derivatives can be computed with only constant overhead, in planar or formula architectures, simultaneous computation of all derivatives can require superlinear or nearly quadratic size.

5. Practical Design and Implementation Strategies

Practical approaches for synthesizing multi-output planar circuits incorporate optimization and inverse design:

Photonic routing manifolds use vertically integrated waveguide planes and tap-and-transition devices to realize $10\times100$ multi-output interconnects with mean error $<$ 1 dB (Chiles et al., 2018).
MIMO metastructure devices are designed via adjoint-based optimization routines formulated over circuit network solvers, drastically reducing simulation times compared to full-wave solvers (Szymanski et al., 2021).
Multi-output Boolean circuit minimization is addressed via mixed integer nonlinear programming, allowing arbitrary gate types and architectures while guaranteeing minimal gate count (conditional on solver runtime) (Dimopoulos et al., 2021).
Scalable, fully planar placement and routing algorithms for field-coupled nanocomputing eliminate wire crossings, trading off area overhead for signal reliability and scalability—e.g., layouts for up to 149,000 gates versus earlier limits (Hien et al., 11 Apr 2025).

In quantum architectures, planar multilayer superconducting circuits combine lithographic patterning, vacuum gap energy storage, and aperture-mediated coupling to integrate multiple resonator and qubit modes without loss from wire crossings (Minev et al., 2015). In Pfaffian circuit theory, algebraic techniques (e.g., decomposing SWAP gates via basis change and orthogonality) allow limited relaxation of planarity, slightly increasing the expressiveness of multi-output holographic algorithms (Turner, 2015).

6. Theoretical and Applied Implications

The mathematical and algorithmic results on multi-output planar circuits have wide-ranging implications:

They map out the tradeoffs between robust function, minimal complexity, and layout constraints for next-generation circuit design.
The failure of the Baur–Strassen theorem under planarity signals fundamental limits in certain derivative-based computational paradigms.
Exponential locality in memristor arrays and efficient simulation of quantum circuits on planar architectures suggest new hardware optimizations, particularly for large-scale machine learning or quantum information processors.
Enumeration results and constructive methods provide both conceptual cataloging of possible designs and actionable algorithms for fabrication and synthesis.

An open direction remains in tightening lower bounds, constructing explicit polynomials maximizing circuit size within planar constraints, and exploiting insights from Boolean theory for the arithmetic setting. The separation between multi-output and single-output complexity, and between formula and circuit classes, underscores the nuanced role of topology in circuit computation and optimization.

7. Future Directions

Continued research may focus on:

Refined complexity lower bounds using combinatorial and algebraic methods.
Extension of enumerative techniques to mixed-mode or hybrid circuit architectures.
Algorithmic advances for optimization and routing, reducing area and time overhead in FCN and photonic platforms.
Algebraic generalizations of planarity relaxation in tensor network and holographic circuit frameworks.
Exploration of the interplay between circuit topology (planarity), physical implementation constraints, and circuit complexity, particularly for emerging quantum and nanoscale technologies.

These ongoing areas are poised to further illuminate both the theory and practice of multi-output planar circuits—their limits, design spaces, and roles in high-performance, high-reliability applications.