QPU Slicing: Partitioning Quantum Workloads

• QPU slicing is a set of techniques that partition quantum workloads into manageable slices across single or multiple QPUs to optimize resources and performance.
• It involves methods such as logical partitioning within a device, multi-QPU distribution via remote operations, and circuit cutting with classical post-processing.
• The approach balances improved throughput and reduced qubit requirements against increased classical computation and communication overhead.

Searching arXiv for papers on QPU slicing, multi-QPU partitioning, and circuit cutting. QPU slicing denotes a family of techniques for partitioning quantum computational resources so that a workload that would otherwise be executed monolithically is instead realized over smaller logical regions, separate QPUs, or cut subcircuits. Across the literature, the term covers at least three closely related practices: logically partitioning a single device into disjoint slices for concurrent programs, partitioning a circuit across multiple QPUs connected by remote operations, and cutting a circuit into hardware-sized fragments that are reassembled by classical post-processing (Romão et al., 13 Jan 2026, Sarkar et al., 12 May 2026, Tang et al., 2022). The common objective is to reduce pressure on qubit count, connectivity, coherence, or initialization overhead while preserving either throughput, fidelity, or both.

1. Scope and meanings of QPU slicing

A recurring source of ambiguity is that “QPU slicing” is not used uniformly. In neutral-atom multi-programming, slicing means a single chip is logically partitioned into independent “tiles” or “virtual zone layouts,” each hosting a separate circuit (Romão et al., 13 Jan 2026). In cloud scheduling work, slicing means assigning disjoint subsets of physical qubits on one NISQ device to concurrent jobs, possibly with qubit-quality and crosstalk-aware placement (Lu et al., 2024). In modular architectures, slicing means assigning logical qubits and remote gates across multiple QPUs connected by a communication fabric, with the partition evaluated against topology, ports, and congestion (Sarkar et al., 12 May 2026). In circuit cutting, slicing means introducing cuts on wires or gates so that smaller subcircuits fit available QPUs and are later knitted together classically (Tang et al., 2022, Tang et al., 2022, Tang et al., 5 Feb 2025).

This suggests that the unifying concept is not a single mechanism but a single abstraction: a quantum computation is decomposed into resource-bounded slices whose coupling is either forbidden, mediated by remote operations, or reconstructed classically. The distinction matters. Some systems require semantic independence between slices, as in MultiQ’s checker for bundled neutral-atom programs (Romão et al., 13 Jan 2026). Others allow explicit inter-slice communication, as in modular multi-QPU compilers and communication processors (Tham et al., 2022, Li et al., 2 Sep 2025). Still others replace quantum coupling by classical recombination, as in CutQC and TensorQC (Tang et al., 2022, Tang et al., 5 Feb 2025).

2. Single-device slicing and multi-programming

On a single physical QPU, slicing is most explicit in MultiQ’s neutral-atom architecture. MultiQ targets a zoned neutral-atom device with storage, entanglement, and measurement zones, and compiles each circuit not to physical coordinates but to a “virtual zone layout”: an abstract rectangular tile with storage and entanglement sub-zones, width, and height (Romão et al., 13 Jan 2026). For a circuit with $N_q$ qubits, storage rows $N_r$, storage spacing $S_s$, and a performance weight $P_w$, layout width is chosen between the packing width

$$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$

and a wider performance-oriented layout

$$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$

The controller then bundles tiles into bins, places them on the 2D array, schedules movement and gate layers, and exploits “SIMD-like parallelization: a single hardware instruction can operate on qubits belonging to different, independent circuits” (Romão et al., 13 Jan 2026).

The neutral-atom hardware model constrains this slicing directly. MultiQ models a 280-qubit QPU with storage rows, SLM traps, AOD beams, a local blockade-mediated CZ via @rydberg, row-wise $R_Z^R$, and global $R_Y^G$, while also accounting for row-wise, diagonal, and column-wise AOD movement collisions (Romão et al., 13 Jan 2026). Initialization and sorting take approximately $82\,\mathrm{ms}$ per shot on a $250$–$N_r$0-qubit device, whereas circuits up to $N_r$1 qubits have execution times shorter than initialization. This makes slicing primarily a throughput optimization: multiple small circuits can amortize one initialization.

QSRA studies the same idea in a cloud NISQ setting. Jobs are tuples $N_r$2, with $N_r$3 required qubits, $N_r$4 shots, and $N_r$5 submission time, and service time

$N_r$6

Its scheduler uses qubit-aware metrics such as

$N_r$7

and a QHRRF priority

$N_r$8

then allocates connected qubit regions using the connectivity ratio $N_r$9 and the qubit-quality score

$S_s$0

QSRA also merges nearby programs with similar $S_s$1 so that crosstalk-aware scheduling can be applied to the merged program rather than enforced via idle spatial buffers (Lu et al., 2024).

3. Modular multi-QPU slicing

When slices span multiple QPUs, the main issue becomes not initialization amortization but communication structure. QuPort formalizes this with three graphs: a weighted logical interaction graph $S_s$2, a directed physical coupling map inside each QPU, and an undirected QPU-level interconnect graph $S_s$3 (Sarkar et al., 12 May 2026). A partition $S_s$4 induces cross-QPU traffic, boundary qubits, and link load, and TPCCAP optimizes

$S_s$5

The first term penalizes weighted cut distance, the second communication-port overflow, and the third routed link-load congestion. This makes slicing explicitly topology-, port-, and congestion-aware rather than purely cut-minimizing (Sarkar et al., 12 May 2026).

A related line of work treats inter-QPU cost through graph cuts and temporal locality. “Quantum circuit optimization for multiple QPUs using local structure” models the circuit as a coupling graph with Laplacian $S_s$6, then minimizes

$S_s$7

under cardinality constraints for QPU size (Tham et al., 2022). It supplements this with rolling time windows, so the effective partition can change over time when local interaction structure changes. The same work derives a remote CNOT from a shared Bell pair, local CNOTs, Hadamards, measurements, and classical communication, making explicit why inter-QPU gates are the costly resource (Tham et al., 2022).

LarQucut treats distributed slicing as a joint cutting-and-mapping problem. It allows both wire cuts and gate cuts, with classical post-processing and sampling costs

$S_s$8

then introduces “hemicut” pruning: after finding a full partition, it retains only “critical cuts” that substantially reduce remote gates (Dou et al., 28 Feb 2025). It also identifies isomorphic subcircuits for result reuse and uses hotness- and weakness-aware placement to reduce SWAPs and EPR usage.

At the architectural level, QNPU separates local computation from network communication. Each node contains a QPU for local gates and a QNPU for communication qubits, EPR management, and distributed protocols expressed in DistQASM via operations such as teleport, cat_ent, and cat_disent (Li et al., 2 Sep 2025). High-level instructions such as SEND_TP_QUBIT and GET_TP_QUBIT are implemented by micro-operations for EPR reservation, classical messaging, and quantum corrections, providing an execution substrate for fine-grained multi-QPU slicing (Li et al., 2 Sep 2025).

4. Circuit cutting and hybrid slicing

Circuit cutting treats slicing as decomposition of one logical circuit into hardware-sized subcircuits whose joint behavior is reconstructed classically. CutQC performs vertical cuts on qubit wires and reconstructs the full output distribution through a Pauli-basis expansion: $S_s$9 It uses a MIP cut searcher with objective

$P_w$0

thereby making the post-processing blow-up from the number of cuts explicit (Tang et al., 2022). CutQC supports full-definition reconstruction of the entire $P_w$1-dimensional output vector and dynamic-definition reconstruction that recursively refines only selected bins, which is how it reaches 100-qubit-scale studies (Tang et al., 2022).

ScaleQC pursues the same hybrid objective but focuses on larger-than-QPU workloads. It uses a MIP-based DAG partitioner with load factor $P_w$2, minimizes the maximum compute-graph degree $P_w$3, and adds “states merging” so that only coarse-grained bins of the output space are reconstructed at each recursion (Tang et al., 2022). This allows benchmarks up to 1000 qubits and shifts the target from full-state reconstruction to locating high-probability solution states. TensorQC replaces naive classical reconstruction by tensor-network contraction, giving an upper bound

$P_w$4

instead of $P_w$5, and adds Heavy State Selection so that only heavy outputs are retained in the reconstruction pipeline (Tang et al., 5 Feb 2025). It reports execution of six realistic benchmarks up to 200 qubits using QPUs available nowadays and a single GPU, while reducing QPU size and quality requirements by more than $P_w$6 over purely quantum platforms (Tang et al., 5 Feb 2025).

shardQ specializes circuit cutting to encoder circuits and non-all-to-all superconducting hardware. It uses SparseCut, MPS compilation, and global knitting, and cuts CX gates via a Pauli-basis/QPD decomposition such as

$P_w$7

then reconstructs target observables from global correlations rather than only local estimators (Guo et al., 7 Nov 2025). This is a slicing strategy tuned to structured tensor encoders rather than general-purpose circuit graphs.

5. Algorithm-specific slicing and communication bounds

Some slicing schemes are algorithm-structured rather than compiler-structured. In “Parallel circuit implementation of variational quantum algorithms,” slicing is obtained by removing coupling terms $P_w$8 from the quantum Hamiltonian so that

$P_w$9

with each $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$0 acting on a disjoint register (Cattelan et al., 2023). The resulting pQAOA, pVQE, and pQA circuits run on smaller slices, while the removed couplings are evaluated classically in the objective. In symmetric cases, the same work states that “it is also possible to run full VQA models while training parameters using only one slice” (Cattelan et al., 2023). This suggests that for some optimization encodings, slicing is not merely a hardware workaround but a statement about redundancy in the circuit representation.

Hybrid annealing provides another algorithm-specific version. For larger-than-QPU lattice-structured Ising problems, the global Hamiltonian

$$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$1

is sliced into subregions $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$2, and each QPU call solves the conditional subproblem

$$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$3

The boundary interaction is absorbed into effective local fields, and repeated large-neighborhood updates propagate local QPU improvements to the global assignment (Raymond et al., 2022).

A fully worked communication-optimal example is multi-QPU Dicke state preparation. For $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$4 QPUs, each hosting approximately $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$5 qubits, the paper constructs a circuit for $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$6 with communication complexity $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$7, circuit size $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$8, and circuit depth $$W_\text{min} = \left\lfloor \frac{N_q}{N_r} \right\rfloor \cdot S_s$$9 (Chen et al., 28 Jan 2026). It also proves a lower bound

$$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$0

and for $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$1 computes the exact Dicke-state lower bound $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$2, matching the construction (Chen et al., 28 Jan 2026). This is one of the clearest statements in the literature that slicing cost is fundamentally constrained by tensor rank across the partition.

6. Correctness, trade-offs, performance, and limitations

Across these systems, slicing is only useful if the sliced execution remains semantically faithful to the unsliced one. MultiQ makes this explicit with its notion of functional independence: $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$3 checked via circuit reconstruction and ZX-calculus simplification (Romão et al., 13 Jan 2026). In other settings, correctness is statistical rather than exact: circuit cutting reconstructs expectation values or distributions through quasi-probability sums, and its limiting factor is sampling variance and classical post-processing overhead rather than semantic interference (Tang et al., 2022, Tang et al., 5 Feb 2025).

The central trade-off is always between smaller slices and more overhead. In MultiQ, narrower neutral-atom slices improve spatial utilization and throughput but create more movement conflicts and sub-rounds, which slightly increases decoherence; wider slices do the opposite (Romão et al., 13 Jan 2026). In QSRA, strict spatial buffers reduce crosstalk but waste qubits, whereas merging nearby jobs improves utilization at the price of co-compilation complexity (Lu et al., 2024). In circuit cutting, more cuts reduce per-QPU width and depth but induce exponential classical factors such as $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$4, $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$5, or large tensor-network contractions (Tang et al., 2022, Dou et al., 28 Feb 2025, Tang et al., 5 Feb 2025). In modular multi-QPU systems, fewer cuts may leave more remote gates, while more aggressive partitioning may overflow ports or congest links (Sarkar et al., 12 May 2026).

Reported performance gains are therefore heterogeneous rather than uniform. MultiQ shows a throughput increase from $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$6 to $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$7 when multi-programming 4 to 14 circuits, with fidelity ranging from a $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$8 improvement for four circuits to only a $$W_\text{selected} = P_w \cdot W_\text{best} + (1 - P_w)\cdot W_\text{min}.$$9 loss for fourteen circuits (Romão et al., 13 Jan 2026). MILQ reports a total improvement of up to $R_Z^R$0 in makespan for heterogeneous clusters of QPUs (Seitz et al., 2023). CutQC reports $R_Z^R$1 to $R_Z^R$2 average reduction in $R_Z^R$3 loss relative to direct runs in its hardware study (Tang et al., 2022). LarQucut reduces cuts by $R_Z^R$4–$R_Z^R$5, reduces EPR pairs by $R_Z^R$6, and reduces absolute error by up to $R_Z^R$7 relative to its baselines (Dou et al., 28 Feb 2025). TensorQC reduces QPU size and quality requirements by more than $R_Z^R$8 over purely quantum platforms (Tang et al., 5 Feb 2025). These results are not directly comparable because they optimize different bottlenecks—throughput, turnaround time, communication, tensor contraction cost, or fidelity.

Several limitations recur. MultiQ assumes a zoned neutral-atom architecture with one entanglement zone and supports no cross-slice gates (Romão et al., 13 Jan 2026). QSRA does not provide a formal security or isolation model (Lu et al., 2024). QuPort is a compiler-level abstraction and “does not claim a calibrated hardware runtime or an implementation of a physical remote-gate protocol” (Sarkar et al., 12 May 2026). QNPU evaluates performance without an explicit noise model for teleportation, EPR generation, or network links (Li et al., 2 Sep 2025). Circuit-cutting frameworks still inherit exponential dependence on cut structure in the worst case, even when tensor networks or state-merging reduce the practical exponent (Tang et al., 2022, Tang et al., 2022, Tang et al., 5 Feb 2025). The literature therefore does not support a single claim that slicing is universally beneficial; rather, it shows that slicing becomes advantageous when its added communication, routing, or classical-reconstruction overhead is smaller than the hardware bottleneck it removes.