Photonic Tensor Units: Optical Tensor Processing

• Photonic Tensor Units are integrated photonic processors that perform linear tensor operations like matrix and convolution computations using optical signals.
• Multiple architectures—including passive in-memory, homodyne, and fully multiplexed designs—enable high-throughput, low-latency dense linear operations.
• PTUs address challenges such as calibration, insertion loss, and precision trade-offs while innovations in materials and design automation foster scalable photonic computing.

Photonic Tensor Units (PTUs) are integrated photonic processors that execute tensor primitives—most commonly matrix–vector multiplication, matrix–matrix multiplication, and convolution—by mapping digital tensors onto optical carriers and performing multiply–accumulate operations in the optical or mixed optical–electrical domain. Across the literature, PTUs are described as the photonic analog of electronic tensor cores or TPUs, but the term covers multiple implementation regimes: passive wavelength-division-multiplexed in-memory crossbars, coherent homodyne crossbars, polarization-domain processors, microring-based mixed-signal arrays, and fully multiplexed tensor fabrics. Their unifying property is specialized acceleration of dense linear operations at high bandwidth and low latency, with throughput determined by photonic parallelism and electro-optic I/O rather than by conventional charge-based arithmetic alone (Feldmann et al., 2020, Nie et al., 15 Jun 2026, Peserico et al., 2022).

1. Definition and conceptual scope

In the strictest sense, a PTU is a programmable photonic core that realizes linear tensor mappings on optical signals. This includes the canonical neural-network primitive $y = W x$, batched extensions such as GEMM, and convolutional operators that are either lowered to matrix multiplication or implemented directly as tensor flows. The review literature places PTUs within the broader class of programmable photonic unitary circuits, where arbitrary linear maps are assembled from unitary transformations and diagonal amplitude or phase weighting, often via singular value decomposition $M = U \Sigma V^\dagger$ (Kim et al., 2024, Peserico et al., 2022).

The designation is broader than a single hardware template. In passive in-memory designs, weights are stored locally in nonvolatile photonic memory and inputs are broadcast over many wavelengths. In homodyne designs, multiplication is enacted by coherent interference and balanced detection, and accumulation is transferred to time-integrating electronics. In polarization-domain designs, the product is encoded in Stokes parameters rather than amplitude alone. In fully multiplexed designs, one programmed operator is broadcast simultaneously across wavelength, RF subcarrier, guided mode, time, and space (Feldmann et al., 2020, Nie et al., 15 Jun 2026, Shafiee et al., 31 Jan 2025, Sun et al., 24 Apr 2026).

The term also admits a looser usage. In photonic logic tensor computing, “tensor” refers to multi-channel, multi-dimensional transformations over wavelength and space rather than to linear-algebra tensor contraction. The photonic universal logic tensor core therefore falls under the PTU umbrella, but it targets reconfigurable Boolean logic rather than dense numerical GEMM (Zhang et al., 29 Apr 2025). A common misconception is that PTUs are synonymous with one specific mesh or crossbar topology; the literature instead presents PTUs as a class of photonic accelerators specialized for tensor kernels, with substantial variation in encoding, accumulation, programmability, and precision.

2. Computational principles

The central PTU operation is optical realization of a weighted sum. In passive wavelength-multiplexed in-memory designs, each input element $x_i$ is encoded on the amplitude of an optical field $E_i(\lambda_i)$, while each matrix weight $w_{ij}$ is stored as a transmission coefficient $T_{ij}(\lambda_i)$ set by a local phase-change-memory element. The detected current at column $j$ scales as

$$I_{\mathrm{pd},j} \propto \sum_{i=1}^{n} \left|T_{ij}(\lambda_i)\,E_i(\lambda_i)\right|^2,$$

and, under channel isolation and broadband non-resonant routing assumptions, the output approximates

$y_j \approx \alpha \sum_{i=1}^{n} w_{ij}\,x_i,$

with $\alpha$ fixed by passive fan-out and fan-in losses (Feldmann et al., 2020).

Homodyne PTUs replace incoherent power summation with coherent mixing. For optical fields $M = U \Sigma V^\dagger$0 and $M = U \Sigma V^\dagger$1 encoding data and weights, balanced detection isolates the mixing term

$M = U \Sigma V^\dagger$2

which, under amplitude encoding and controlled relative phase, yields signed multiplication $M = U \Sigma V^\dagger$3. Time integration over a window then produces a MAC,

$M = U \Sigma V^\dagger$4

and spatiotemporal interleaving accumulates a sequence of outer products into MVM or GEMM (Nie et al., 15 Jun 2026). Large homodyne crossbars extend the same principle to arrays of balanced homodyne units, with time multiplexing reducing the high-speed modulator count from $M = U \Sigma V^\dagger$5 to $M = U \Sigma V^\dagger$6 while the photonic array performs $M = U \Sigma V^\dagger$7 multiplications in parallel (Zhou et al., 20 Apr 2026).

Convolution enters in two distinct ways. One route is the standard im2col or Toeplitz transformation, which maps each sliding window to an input vector $M = U \Sigma V^\dagger$8 and applies $M = U \Sigma V^\dagger$9. The other is direct tensor flow, in which wavelength, time delay, and space are assigned to tensor axes so that the input tensor “flows” through delay-weight-sum hardware without tensor–matrix unfolding (Feldmann et al., 2020, Xu et al., 2021). Fully multiplexed PTUs generalize this further: a single programmed operator $x_i$0 is applied pointwise to an input tensor spanning input port, RF subcarrier, wavelength, guided mode, and time,

$x_i$1

thereby turning orthogonal field dimensions into multiplicative parallelism (Sun et al., 24 Apr 2026).

3. Major architectural families

The PTU literature now spans several architectural lineages distinguished by where multiplication occurs, how accumulation is implemented, and how weights are programmed.

Family	Distinguishing mechanism	Representative work
Passive in-memory WDM crossbar	Soliton microcomb inputs, SiN crossbar, PCM weights, incoherent detection	(Feldmann et al., 2020)
Homodyne crossbar	Coherent interference, balanced PDs, time-integrating array, $x_i$2 interfaces	(Nie et al., 15 Jun 2026)
Large-scale homodyne GEMM array	256×256 homodyne units, time multiplexing, TFLN transmitters	(Zhou et al., 20 Apr 2026)
Polarization-domain PTU	SnSe phase shifters, TE/TM Jones vectors, Stokes-parameter readout	(Shafiee et al., 31 Jan 2025)
Microring mixed-signal tensor core	Differential pSRAM-controlled MRR weights with integrated eoADC	(Kaiser et al., 28 Jun 2025)
Direct tensor-flow processor	Wavelength–time–space mapping without tensor–matrix transformation	(Xu et al., 2021)
Fully multiplexed tensor core	Uniform operator across wavelength, RF, guided mode, time, and space	(Sun et al., 24 Apr 2026)
Topological ferroelectric PTU	Cascaded SSH-cavity PZT modulators with nonvolatile GHz-rate programming	(Zhou et al., 5 Nov 2025)

Passive in-memory PTUs emphasize local weight storage and extremely low dynamic core energy. The integrated photonic tensor core based on soliton microcombs, passive SiN routing, and GST phase-change cells uses optical transmission as the multiply primitive and photodetection as the accumulator. Because the routing elements are non-resonant and broadband, the computation reduces largely to calibrated attenuation and summation (Feldmann et al., 2020).

Homodyne PTUs address a different bottleneck: the scaling of electro-optic write/read interfaces and optical beam-combining loss. The spatiotemporally interleaved homodyne photonic tensor core routes data horizontally and weights vertically, performs local multiplication by coherent detection, accumulates charge on capacitors, and serializes readout over buses. This preserves $x_i$3 parallel multiplications in an $x_i$4 matrix while reducing high-speed DACs, modulators, and ADC channels to $x_i$5 (Nie et al., 15 Jun 2026). A closely related but much larger coherent homodyne platform demonstrates 256 × 256 units on a single reticle and explicitly targets general GEMM at 20–128 Gbaud/s (Zhou et al., 20 Apr 2026).

Other PTUs depart more radically from the passive crossbar template. WPol-PTC uses wavelength multiplexing plus polarization-domain computing, with programmable SnSe ferroelectric phase shifters setting Jones-matrix transformations whose products are read back from reconstructed Stokes parameters (Shafiee et al., 31 Jan 2025). The mixed-signal pSRAM-based tensor core stores weights in differential photonic SRAM cells that drive microrings and digitizes the accumulated analog output through a one-hot electro-optic ADC (Kaiser et al., 28 Jun 2025). FieldCore uses inverse-designed silicon photonics to preserve one programmed crossbar operator across wavelength, RF subcarrier, guided mode, time, and space, rather than using only one or two multiplexing axes (Sun et al., 24 Apr 2026). The topological accelerator based on ferroelectric PZT thin films pushes reconfiguration into the GHz electro-optic regime while maintaining nonvolatile states and topological confinement (Zhou et al., 5 Nov 2025).

4. Throughput, density, latency, and efficiency

Reported PTU performance spans from hundreds of GOP/s to multi-thousand-TOPS regimes, but these figures are architecture-specific and use different operation-counting conventions. The integrated photonic tensor core for convolution reported $x_i$6 for a 9×4 matrix with four parallel vectors at 14 GHz modulation, with operating bandwidth exceeding 14 GHz and optical core latency effectively sub-nanosecond (Feldmann et al., 2020). The photonic tensor flow processor reported 480 GOP/s, or about 240 GMAC/s, at 20 GHz with a compute density of 588 GOP/s/mm² (Xu et al., 2021).

Homodyne designs substantially extend the upper end of the throughput envelope. The spatiotemporally interleaved homodyne photonic tensor core demonstrated a 4×4 array on thin-film lithium niobate, with folded traveling-wave modulators exhibiting a measured $x_i$7 EO bandwidth of 37.8 GHz and a multiplication benchmark residual standard deviation of 0.0621 over $x_i$8 (Nie et al., 15 Jun 2026). The larger coherent homodyne GEMM system reported 1,000–6,000 TOPS aggregate throughput, 7-bit computational accuracy across 8×8 parallel channels at 120 Gbaud/s, 6-bit statistical accuracy across 256×100 channels at 20–128 Gbaud/s, and about 330 TOPS/W when memory, ADC, and nonlinear post-processing were included (Zhou et al., 20 Apr 2026).

Microring and topological implementations occupy intermediate but still high-throughput points. The mixed-signal pSRAM-based tensor core in GlobalFoundries 45SPCLO reported 4.10 TOPS and 3.02 TOPS/W, with a 3-bit eoADC operating at 8 GS/s (Kaiser et al., 28 Jun 2025). The time–space–wavelength multiplexed coherent crossbar reported 0.96 TOPS for a 4×2×1 tensor–vector multiplication unit at 60 GBd, with an average error of 3.9% (Kovaios et al., 13 May 2026). The fully multiplexed FieldCore architecture reported an estimated 69.12 TOPS and support for up to 1,800 parallel input streams within a single core (Sun et al., 24 Apr 2026). The wafer-scale ferroelectric topological accelerator reported 1.92 TOPS, 266 TOPS/mm², and 265 fJ/OP for a 16-channel wavelength-space-multiplexed chip (Zhou et al., 5 Nov 2025).

These figures should not be read as directly interchangeable. A plausible implication is that throughput depends not only on photonic device bandwidth, but also on the chosen parallel axes, the definition of an operation, the analog precision target, and whether DAC/ADC, memory traffic, and electronic nonlinearities are included in the accounting. Several papers make this explicit by showing that converter overhead, optical insertion loss, or memory bandwidth dominate system-level scaling once the core photonic MAC is no longer the bottleneck (Tomich et al., 19 Sep 2025, Alo et al., 16 Apr 2026).

5. Precision, programmability, and demonstrated workloads

PTUs are analog or mixed-signal accelerators, so precision is set by optical noise, modulator linearity, detector noise, calibration quality, and device drift rather than by a fixed digital word length. In the passive SiN/PCM tensor core, 100,000 dot products produced an error standard deviation of 0.008, corresponding to approximately 5-bit resolution, while closed-loop programming yielded more than 8-bit weight precision for matrix elements (Feldmann et al., 2020). The large homodyne GEMM system reported up to 7-bit computational accuracy in smaller parallel configurations and 6-bit statistical accuracy in larger ones (Zhou et al., 20 Apr 2026). FieldCore and the topological PZT accelerator both operated at about 5-bit effective precision in their task-level demonstrations (Sun et al., 24 Apr 2026, Zhou et al., 5 Nov 2025).

Weight programmability varies by material stack. GST and GSSe phase-change elements provide nonvolatile multilevel attenuation without static hold power (Miscuglio et al., 2020, Feldmann et al., 2020). SnSe ferroelectric phase shifters offer sub-0.1 ns switching speed, programming voltage below 0.5 V, and effectively zero static power after programming (Shafiee et al., 31 Jan 2025). Differential pSRAM cells provide electrically stored, fast-updating microring weights within a CMOS-compatible silicon photonics node (Kaiser et al., 28 Jun 2025). PZT thin films provide nonvolatile resonance tuning with 23 distinct states over a 3 nm range and no sustaining bias (Zhou et al., 5 Nov 2025). This diversity shows that “photonic memory” in PTUs is not a single device class but a design dimension spanning nonvolatile phase-change attenuation, ferroelectric state control, and electrically latched resonant tuning.

The workload record is already broad. The passive integrated photonic tensor core executed a 2 GHz optically accelerated MNIST CNN with 95.3% accuracy versus 96.1% for a digital baseline and 8.1 µs/image latency (Feldmann et al., 2020). The direct tensor-flow processor reached 97.9% accuracy on KTH action recognition (Xu et al., 2021). The TSWDM coherent crossbar reported 93.3% accuracy on the Iris dataset at 4×10–4×30 GBd (Kovaios et al., 13 May 2026). The topological PZT accelerator reported 95.64% digit-recognition accuracy and 94.5% precision for solving time-varying partial differential equations (Zhou et al., 5 Nov 2025). FieldCore reported 93.8% accuracy on parallel MNIST, 90.8% on Indian Pines hyperspectral classification, and 95.1% on CWRU mechanical fault diagnosis (Sun et al., 24 Apr 2026).

System software is emerging alongside hardware. ADEPT introduced a differentiable search framework for photonic tensor cores, reporting 2×–30× higher footprint compactness and better noise robustness than prior manually designed structures under foundry constraints (Gu et al., 2021). LightCode raised PTUs to first-class compilation targets for hybrid photonic–electronic LLM inference, with simulated photonic offload yielding up to 50% energy reduction at maximum sequence length and abstract-level latency improvements exceeding 10×, while also noting that under some modeled scenarios PTU offload did not reduce latency because conversion and bandwidth bottlenecks dominated (Tomich et al., 19 Sep 2025). That tension is a central system-level result rather than a contradiction: energy-optimal PTU placement and latency-optimal PTU placement need not coincide.

6. Limitations, misconceptions, and research directions

A persistent misconception is that PTUs already provide end-to-end all-optical neural networks. In most reported systems, the photonic core performs only the linear MAC-heavy stage, while nonlinear activations, softmax, recurrent updates, normalization, ADC/DAC boundaries, and scheduling remain electronic (Feldmann et al., 2020, Peserico et al., 2022, Tomich et al., 19 Sep 2025). Another misconception is that optical throughput alone determines system advantage. Multiple studies show that DAC/ADC energy, memory bandwidth, readout serialization, detector noise, and optical distribution loss can dominate once the core itself becomes sufficiently fast (Nie et al., 15 Jun 2026, Tomich et al., 19 Sep 2025, Alo et al., 16 Apr 2026).

The main technical constraints recur across architectures. Passive WDM crossbars confront insertion loss from fan-out and fan-in, wavelength-dependent splitting, and matrix-size scaling (Feldmann et al., 2020). Microring systems face resonance drift, filter crosstalk, and thermal calibration burdens (Kaiser et al., 28 Jun 2025). Homodyne systems must manage phase stability, balanced detector noise, and integrator scaling even as they remove intrinsic beam-combining loss (Nie et al., 15 Jun 2026, Zhou et al., 20 Apr 2026). Polarization-domain systems reduce coherent interference accumulation but still require calibration for PBS crosstalk, MRR loss, and SnSe variability (Shafiee et al., 31 Jan 2025). Fully multiplexed systems gain multiplicative parallelism, but RF bandwidth and per-channel SNR eventually limit channel count (Sun et al., 24 Apr 2026).

Research directions therefore concentrate on three fronts. First, architectural scaling: unary and homodyne accumulation are identified as particularly favorable for large parallelism under common optical power models, while spatiotemporal interleaving reduces electrical interface growth from $x_i$9 to $E_i(\lambda_i)$0 (Alo et al., 16 Apr 2026, Nie et al., 15 Jun 2026). Second, device and materials scaling: topological ferroelectric PZT, thin-film lithium niobate, low-loss SiN, phase-change materials, and inverse-designed multimode components are all being used to improve bandwidth, compactness, and static-power characteristics (Zhou et al., 5 Nov 2025, Nie et al., 15 Jun 2026, Sun et al., 24 Apr 2026). Third, design automation and compilation: differentiable topology search, hardware-aware training, and compiler-level graph assignment are increasingly necessary because PTU performance is inseparable from calibration strategy, converter placement, and workload scheduling (Gu et al., 2021, Tomich et al., 19 Sep 2025).

Taken together, the literature defines PTUs not as a single device, but as a rapidly diversifying hardware category for tensor primitives in which optical multiplexing, local analog physics, and electronic control are co-designed. The reported systems already cover convolutional inference, GEMM, direct tensor processing, logic computing, PDE solving, hyperspectral classification, and hybrid LLM compilation. This suggests that the long-term significance of PTUs will depend less on whether one architecture dominates, and more on whether photonic tensor processing can be embedded into complete compute stacks with controlled precision, manageable converter overhead, and scalable programming models.