SC-PCC Decoder: Efficient Iterative Threshold Decoding

• PCCC decoders are low-complexity iterative threshold decoders for turbo-like code constructions that use convolutional self-orthogonal component codes (CSOCs) for robust error correction.
• Spatial coupling divides information blocks into staggered sub-blocks, enabling sliding-window iterative decoding to attain near-MAP threshold performance with reduced latency.
• The SC-PCC architecture achieves significant coding gains and hardware efficiency by combining APP threshold decoding with scalable linear complexity and parallel processing.

A Parallel-Concatenated Code (PCC) decoder, and specifically its spatially coupled variant (SC-PCC), constitutes a class of low-complexity iterative threshold decoders designed for turbo-like code constructions. When equipped with convolutional self-orthogonal component codes (CSOCs) and suboptimal a posteriori probability (APP) threshold decoding, the SC-PCC decoder approaches the maximum a posteriori (MAP) performance threshold and achieves significant coding gains with reduced power, latency, and implementation complexity relative to optimal algorithms (Cummins et al., 2021).

1. Code Structure and Spatial Coupling

SC-PCCs are constructed using parallel concatenation of two CSOCs, each encoding a distinct permutation of the input. Each CSOC is a rate-$R_c = \frac{k}{k+1}$ systematic convolutional code defined by constraint length $\nu = k(m+1)$ and memory $m$. Self-orthogonality ensures that for each information error bit $e^{(i)}_l$, there are $J$ parity-check equations $A_j^{(i)}$, with no other error bit involved in more than one check. This structure guarantees a threshold decoding error-correction capability of $\lfloor J/2 \rfloor$.

Example parameterization for a rate-$2/3$ CSOC:

• $k=2$, $m=13$, $\nu = k(m+1)$0
• Generator sequences (octal):
  • $\nu = k(m+1)$1
  • $\nu = k(m+1)$2
• $\nu = k(m+1)$3, code rate $\nu = k(m+1)$4

Spatial coupling is realized by dividing each information block $\nu = k(m+1)$5 (length $\nu = k(m+1)$6) into $\nu = k(m+1)$7 sub-blocks, forming a “coupled source matrix” $\nu = k(m+1)$8 such that each column is constructed from staggered sub-blocks across time and coupling depth. The matrix is zero-padded at boundaries, facilitating coupling across $\nu = k(m+1)$9 blocks. Parallel interleaving and demultiplexing generate a permuted matrix $m$0.

At encoder output, for each time $m$1, both $m$2 and $m$3 are encoded by their respective CSOCs (each terminated by $m$4 zeros), resulting in parity outputs $m$5 and $m$6 concatenated with the systematic output $m$7: $m$8 The overall SC-PCC code rate is $m$9 for $e^{(i)}_l$0.

2. APP Threshold Decoding of CSOCs

Threshold decoding for CSOCs involves syndrome formation, LLR computation, and weighted thresholding:

1. Syndrome Formation: For each received symbol $e^{(i)}_l$1, a hard decision $e^{(i)}_l$2 is made. The error bit $e^{(i)}_l$3 is computed. The syndrome is:

$e^{(i)}_l$4

2. LLR (Reliability Factor):

$e^{(i)}_l$5

where $e^{(i)}_l$6 includes any a priori LLR from external decoder feedback.

3. Self-Orthogonal Check Weighting: For each check $e^{(i)}_l$7, the extrinsic weight is formed:

$e^{(i)}_l$8

using the box-plus operation.

4. Threshold Decision Rule: The decoded estimate is:

$e^{(i)}_l$9

where the full LLR argument includes self-orthogonal check extrinsic weight sums.

3. Sliding-Window Iterative Decoding Algorithm

The SC-PCC decoding algorithm employs a windowed message-passing procedure:

• A window size $J$0 is selected, targeting block $J$1.
• The received data for $J$2 contiguous blocks is demultiplexed into coupled channel inputs for the two parallel streams.
• Two APP threshold decoders process their respective streams, exchanging extrinsic LLRs per block via turbo-style iterations.

The schedule is divided into vertical iterations ($J$3 forward sweeps per block) and horizontal iterations ($J$4 full forward-reverse sweeps). For each target block,

$J$5

component decoder calls are made. Hard decisions are output after $J$6 horizontal iterations or on successful CRC.

Pseudocode (verbatim from (Cummins et al., 2021)):

$k=2$7

4. Latency, Memory, and Complexity

Latency

• Encoding: Requires buffering $J$7 input blocks, leading to latency $J$8.
• Decoding: Windowed decoding of size $J$9 adds latency $A_j^{(i)}$0. Minimum window for $A_j^{(i)}$1 is $A_j^{(i)}$2.

Memory

• Encoder memory: $A_j^{(i)}$3; for uncoupled PCC: $A_j^{(i)}$4.
• Decoder memory: Buffer for extrinsic LLRs $A_j^{(i)}$5, interleaver $A_j^{(i)}$6, syndrome/channel value registers per component $A_j^{(i)}$7; total $A_j^{(i)}$8.

Computational Complexity

• For block length $A_j^{(i)}$9, average nonzero taps per generator $\lfloor J/2 \rfloor$0 with $\lfloor J/2 \rfloor$1:

Operation	Per Component Decoder
Multiplications	$\lfloor J/2 \rfloor$2
Additions	$\lfloor J/2 \rfloor$3
Box-plus ops	$\lfloor J/2 \rfloor$4

Total for sliding window: $\lfloor J/2 \rfloor$5

No BCJR trellis is employed, so the complexity scales linearly in $\lfloor J/2 \rfloor$6. Parallelism is possible by decoding $\lfloor J/2 \rfloor$7 information bits simultaneously ahead of syndrome updates.

5. Performance and Threshold Saturation

Performance evaluation in (Cummins et al., 2021) demonstrates:

• For rate $\lfloor J/2 \rfloor$8 ($\lfloor J/2 \rfloor$9), SC-PCC ($2/3$0) achieves a $2/3$1 gain over standard PCC at BER $2/3$2 with similar complexity and latency.
• For rate $2/3$3 ($2/3$4), SC-PCC ($2/3$5) exhibits a $2/3$6 improvement at BER $2/3$7, and increasing $2/3$8 to $2/3$9 yields $k=2$0 gain.

Spatial coupling leads to threshold saturation: the iterative decoder’s waterfall region approaches the MAP threshold of the base PCC ensemble, and increases in coupling memory ($k=2$1) or decoding window ($k=2$2) further advance performance at the cost of higher latency and memory demands. A window $k=2$3 is generally sufficient to exploit most coupling gains. Excessively large $k=2$4 can degrade LLR reliability due to edge effects, which may be mitigated by LLR scaling or optimized message-passing schedules.

6. Hardware and Implementation Considerations

The SC-PCC decoder enables efficient VLSI design due to several attributes:

• Linear complexity in constraint length $k=2$5, avoiding the computational intensity of BCJR-based trellis decoding.
• High natural parallelism, as $k=2$6 information bits are independently threshold-decoded prior to syndrome updates.
• Hardware operations are restricted to additions, comparisons, and box-plus computations, precluding the need for exponentiation or division, resulting in reduced power consumption.

7. Significance and Broader Impact

The SC-PCC decoder with CSOC components and APP threshold decoding achieves notable coding gains over uncoupled PCCs at equivalent complexity and latency by leveraging spatial coupling. The resulting threshold saturation phenomenon demonstrates that performance can approach theoretical MAP limits using practical, scalable decoding rules. This framework highlights the utility of spatial coupling in enhancing the performance of turbo-like constructions while maintaining architectural efficiency (Cummins et al., 2021).