QC-LDPC JSCC: Robust Joint Coding

• The paper introduces a QC-LDPC JSCC framework that employs dual protograph designs to optimize encoding complexity and achieve near-capacity performance.
• It leverages a two-stage lifting process and triangular linking matrices, improving channel thresholds by up to 0.41 dB and reducing source symbol error rates.
• The design supports hardware-efficient implementation with FPGA prototyping, using 6-bit fixed-point quantization and layered sum-product decoding for low-latency applications.

Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code-based Joint Source-Channel Coding (JSCC) encompasses structural, algorithmic, and hardware advances in the implementation of integrated source and channel coding, targeting efficient, robust, and near-capacity communications for next-generation semantic and task-driven services. By leveraging quasi-cyclic LDPC constructions and refined protograph linking, QC-LDPC-based JSCC schemes achieve favorable trade-offs between code rate, encoding/decoding complexity, and error resilience, facilitating deployment in constrained edge devices and latency-sensitive applications (Zhong et al., 2023, Zhan et al., 2023).

1. Code Construction and Protograph Design

QC-LDPC-based JSCC schemes construct their codes starting from two optimized protograph LDPC base matrices: one for source compression ($\mathbf B_{s1}$) and one for channel protection ($\mathbf B_{c1}$). For example, (Zhong et al., 2023) uses $50\times90$ base matrices from [Chen et al., IEEE Trans. Commun., 2018], achieving a decoding threshold of $-2.1$ dB. The composite block-structured parity-check matrix is built as: $$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$ with the linking block $$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$.

Subsequent two-stage lifting transforms this base to a scalable, hardware-suited QC-LDPC code. Each “1” is replaced by a $z\times z$ circulant permutation matrix (CPM; $z=160$), while “0” entries become all-zero blocks, producing

$$\mathbf H_{QC} = \begin{pmatrix} \mathbf H_{sQC}(3200\times6400) & \mathbf H_{LQC}(3200\times8000) \ \mathbf{0}(4800\times6400) & \mathbf H_{cQC}(4800\times8000) \end{pmatrix}.$$

The resulting source compression ratio is $R_s=2$, channel code rate $\mathbf B_{c1}$0, leading to an overall JSCC code rate $\mathbf B_{c1}$1. The generator matrix $\mathbf B_{c1}$2 underlying the end-to-end mapping is implicitly realized via the block structure, supporting efficient parity computation and systematic encoding for hardware.

Advances from (Zhan et al., 2023) employ a double-protograph structure with refined “linking” submatrices. The traditional identity-based SCCV linking is replaced with a lower- or upper-triangular submatrix, $\mathbf B_{c1}$3, providing design flexibility: $\mathbf B_{c1}$4 This enables up to $\mathbf B_{c1}$5 dB improvement in channel threshold and $\mathbf B_{c1}$6 dB reduction in source symbol error rate (SSER) at SSER $\mathbf B_{c1}$7.

2. Encoder Design, Mapping, and UEP

The encoder first maps the semantic source vector $\mathbf B_{c1}$8 to a compressed binary sequence via $\mathbf B_{c1}$9, yielding $50\times90$0 bits, which are then encoded by the channel LDPC block to form an $50\times90$1-bit codeword. The overall end-to-end mapping is formalized as: $50\times90$2 where $50\times90$3 is an interleaver. For semantic communication, Unequal Error Protection (UEP) is critical; “critical” source bits (e.g., image keypoints) are strategically positioned through $50\times90$4 to correspond to variable nodes of higher degree in the parity-check graph, leveraging node degree diversity for stronger protection. De-interleaving follows decoding to restore original bit ordering and UEP.

A double-stage lifting, typically a graph-constrained PEG lift ($50\times90$5) and a large QC lift ($50\times90$6), consolidates the design for practical implementation and facilitates circulant-based encoding/decoding.

3. Layered Decoding Algorithms and Inter-Module Messaging

QC-LDPC decoding for JSCC systems utilizes a layered sum-product algorithm adapted to the two-subgraph structure of the composite matrix, with iterative message exchange between the source and channel components. The node update schedule follows:

• Variable-to-check update:

$50\times90$7

• Check-to-variable update via the min–sum or hyperbolic tangent rule:

$50\times90$8

• Inter-decoder messaging (at punctured nodes $50\times90$9):

$-2.1$0

A posteriori LLR for bit $-2.1$1 is $-2.1$2. Early stopping is triggered on convergence or after maximum iterations, with hard decisions based on LLR sign.

4. Hardware Implementation and Quantization

A prototypical hardware realization uses a Xilinx Virtex UltraScale+ FPGA platform integrated with RISC-V and neural network accelerators. The QC-LDPC structure enables a single-group layered decoder configuration ($-2.1$3) with 20 layers of 160 CNs per subgraph and fully pipelined block-parallel processing per layer.

The decoder data path is quantized to 6-bit fixed-point (“Proposed-Q6”), replacing floating-point arithmetic. Small LUTs approximate the $-2.1$4 function, further reducing complexity. Additional parity bits are used to mitigate performance losses due to quantization. The entire decoder occupies $-2.1$533% of LUTs and FFs, only 1.4% of BRAMs, and achieves an iteration of the full layered schedule in 31 ms at 100 MHz clock frequency (Zhong et al., 2023).

In the encoding process, the sequential XOR operations corresponding to the triangular linking structure ensure linear complexity in the source block length ($-2.1$6), enabling scalable and high-throughput realization (Zhan et al., 2023).

5. Performance and Comparative Analysis

Quantitative evaluation of QC-LDPC JSCC demonstrates robust BER performance over AWGN, with the 6-bit (“Proposed-Q6”) and floating-point (“Proposed-FP32”) implementations exhibiting comparable curves within 0.2–0.3 dB separation at code rate $-2.1$7 and frame length $-2.1$8. At low SNR ($-2.1$9 to $$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$0 dB), throughput and robustness significantly surpass separate source-channel coding (SSCC) baselines, which require lower code rates ($$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$1) to maintain similar BER. Representative performance summary (SSER at $$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$2) is provided below for the triangular-linking double-protograph design (Zhan et al., 2023):

Example	Rate $$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$3	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$4	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$5	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$6 Threshold
Ex. 1	1	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$7 dB	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$8 dB	$$\mathbf H_{50\times90} = \begin{pmatrix} \mathbf H_{s}(20\times40) & \mathbf H_L(20\times50) \ \mathbf{0}(30\times40) & \mathbf H_{c}(30\times50) \end{pmatrix},$$9 dB
Ex. 2	2	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$0 dB	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$1 dB	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$2 dB
Ex. 3	1	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$3 dB	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$4 dB	$$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$5 dB

A comparison with AR4JA-JSCC and AR3A-JSCC codes indicates that the optimized triangular-linking double-protograph construction can achieve or surpass their threshold and error floor performance while delivering lower encoding complexity (Zhan et al., 2023).

6. Design Guidelines, Trade-offs, and Future Prospects

Designers balance channel threshold and encoding complexity primarily through the choice of linking structure ($$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$6 vs $$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$7), size of lifting parameters ($$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$8, $$\mathbf H_L=[\mathbf 0_{20\times30}\;\mathbf I_{20\times20}]$$9), and detailed configuration of non-diagonal entries in $z\times z$0. The introduction of a triangular linking matrix introduces only a minimal complexity rise but yields substantial threshold gains up to 0.41 dB, making this trade-off favorable for high-reliability, real-time systems.

Future research directions identified in (Zhong et al., 2023) include:

• Collaborative edge-AI JSCC parameter tuning using federated learning and semantic feedback.
• Integration of binarized neural semantic encoders with QC-LDPC to reduce edge device power budget.
• Hybrid models combining data-driven deep-JSCC and QC-LDPC structure for adaptive, end-to-end learning.
• Security and privacy analyses: UEP JSCC robustness against eavesdropping, differential privacy, and adversarial manipulation.

QC-LDPC-based JSCC thus underpins scalable, UEP-capable, low-latency coding and decoding frameworks, anticipated to serve as a foundation for 6G semantic communications, federated inference, and other emerging task-oriented wireless systems (Zhong et al., 2023, Zhan et al., 2023).