OCSes: Optical Circuit Switches in Photonic Networks

Updated 28 May 2026

Optical Circuit Switches (OCSes) are photonic devices that establish deterministic, all-optical connections without optoelectronic conversion.
They employ diverse technologies like MEMS mirror arrays and silicon photonics to deliver low latency, high bandwidth, and scalable connectivity.
OCSes are crucial for datacenter, HPC, and AI/ML networks by enabling reconfigurable, cost-effective, and fault-tolerant optical interconnects.

Optical Circuit Switches (OCSes) are photonic devices and systems that establish deterministic, all-optical paths between endpoints by directly switching light without optoelectronic conversion or per-packet electronics. OCSes are structurally distinct from electrical packet switches and reconfigurable optical add-drop multiplexers (ROADMs), offering unique advantages in capacity scaling, latency, power, and topology flexibility. They play a central role in next-generation data center, high-performance computing (HPC), and backbone network architectures, especially for large-scale AI and ML clusters where high-bandwidth, low-latency, and reconfigurable point-to-point fabrics are crucial.

1. Architectural Taxonomy and Switch Technologies

OCSes span a diverse class of implementations, from free-space 3D MEMS mirror arrays and silicon photonics (SiPh) MZI matrices, to phase-change, magneto-optic, and hybrid integration platforms. A fundamental architectural distinction exists between switch-centric, transceiver-centric, and modular OCS deployments.

MEMS Mirror Arrays: Used in hyperscale deployments (e.g., Google Palomar OCS), these free-space optics (FSO) based switches provide N×N non-blocking connectivity with sub-2 dB insertion loss, ms-scale reconfiguration (median 1.2 ms, 99p <3 ms), and radix scaling to at least 136×136 ports. Bidirectionality is often achieved via circulators, doubling effective radix while maintaining low loss and tight return/crosstalk budgets (Urata et al., 2022, Jouppi et al., 2023).
Silicon Photonics OCS: Mach–Zehnder interferometer (MZI)-based crossbar or circulant matrices achieve port-embedded switching. Devices like the InfiniteHBD OCSTrx embed a compact switch matrix in each QSFP-DD form factor, supporting up to 800 Gb/s per transceiver with ~0.5 dB/stage IL, ms-class switching, and <15 W power, enabling dense, reconfigurable point-to-multipoint or k-hop ring topologies (Shou et al., 6 Feb 2025).
Wavelength Selective Switch (WSS) and OXC-based: Modular OXCs decompose classical N×N cross-connects into cascaded small-port WSS fabrics, reducing cabling from O(N²) to ~O(N), retaining self-routing and non-blocking per-wavelength operation. Aggregate IL scales with stage count (~20 dB for 4×1×8 modular stages), limited by WSS performance and cabling (Ye et al., 2020).
Electro-/Thermo-Optic Resonant and Magneto-Optic Switches: Tri-layer SiN-on-Si S&S architectures, resonant phase shifters (RPS), and nonreciprocal magneto-optic MZIs achieve ns–μs switching. E-O microdisks attain 5.9 ns reconfiguration and sub-1 pJ/bit energy at modest IL, while MO/TO-integrated Benes networks demonstrate 8-fiber, full-duplex 4×4 switching in 60 ns (Sun et al., 16 Feb 2025, Luo et al., 2024, Tu et al., 24 Sep 2025).

OCS fabrics are either organized as monolithic high-radix devices (N×N), modular multi-stage topologies, or arrays of low-radix switches (ACOS). Each approach makes distinct trade-offs in cost, reconfiguration delay, physical layer performance, and scalability (Amir et al., 19 Feb 2026). The following table summarizes typical technology classes and their defining characteristics:

Technology	Radix scaling	IL/Bandwidth	Switching time
MEMS FSO	64–256 (monolithic)	<2 dB, >800 Gb/s/pt	~1–5 ms
SiPh MZI	8–72 (embedded)	0.5 dB/stage	0.5–1 ms
WSS-based OXC	8–160 (modular)	~20 dB (multi-stage)	>ms
Electro-optic S&S	8–32 (chip-scale)	5–15 dB, >100 GHz BW	~10 ns
Magneto-optic	4–16 (current, scalable)	21–24 dB (net)	~60 ns
Low-radix MEMS	2×2, 1×N (ACOS)	<1 dB	<10 ms

2. Topologies, Control, and Scheduling

OCS-based networks support a wide range of reconfigurable topologies underpinning parallel and distributed computing workloads:

Circulant and k-hop Rings: InfiniteHBD defines reconfigurable k-hop ring topologies with active/standby failover ports. Per-node activation of two external links guarantees bandwidth isolation, while K≥2 achieves bounded fault domains and full bandwidth AllReduce, with waste ratio $W_{\max} \le 2(T/R-1)P_s^K$ (Shou et al., 6 Feb 2025).
Benes, Modular Shuffle, and Meshes: Modular OXC approaches realize Benes-like nonblocking topologies through cascaded small-shuffle, self-routing OXC modules, dramatically reducing cabling, with cabling $\sim$ 2Nn (for N=n·r) and inherent per-wavelength nonblocking (Ye et al., 2020).
Hybrid and Multi-Dimensional Fabrics: Datacenter-scale OCS deployments often employ hybrid architectures, with OCS plus electrical packet switching to balance dynamic and throughput demands. Google’s TPU v4 combines Clos-like Clos/torus topologies, dynamically mapped via OCSs for ML jobs with strict performance, availability, and modularity goals (Jouppi et al., 2023).
Arrays of Cheap OCS (ACOS): OCS modules of low radix assemble arbitrary, job-specific topologies (e.g., ring, torus, expander), with cost scaling in modules not $N^2$ and 8 ms reconfiguration per iteration; ACOS achieves performance matching packet-switched networks on LLM training at >20% lower cost for large clusters (Amir et al., 19 Feb 2026).

Efficient control and scheduling are critical. Spectra, a three-step scheduler for parallel OCSes, decomposes AI traffic matrices into weighted permutations, schedules these across s switches accounting for reconfiguration delays, and load-balances via permutation splitting, achieving near-optimal makespan (1.4–2.4× reduction vs. prior algorithms) (Liang et al., 7 Mar 2026). Controller architectures, e.g., based on ONOS or MV-SDN, coordinate OCS reconfiguration in <1 s for production multi-vendor networks, achieving atomic, concurrent path creation, rollback on partial failure, and event-driven restoration (Takano et al., 2024, Anazawa et al., 28 Jan 2025).

3. Physical-Layer Performance and Device Integration

OCS performance is specified by insertion loss (IL), crosstalk (CT), bandwidth, reconfiguration time, and power per port.

MEMS OCS: Large-scale MEMS switches achieve <2 dB IL (136×136), crosstalk <–40 dB, and <3 ms switching. Integration of circulators allows bidirectional/fiber-doubling but imposes stringent return loss (≤–38 dB) specs due to MPI (Urata et al., 2022).
SiPh and EO/Thermo-optic OCS: Tri-layer Si–SiN–SiN S&S switches realize average 5.2 dB IL (T-O) and 15.1 dB (E-O) on 8×8 fabrics, CT down to –50 dB (nanosecond-class E-O switching, 17.6 μs T-O) (Sun et al., 16 Feb 2025). Ring/MZI elements with EO tuning achieve sub-10 ns (often sub-ns) response, with energy per bit $<0.1$ pJ (Luo et al., 2024).
PCM-based Directional Couplers: 1×2 and 2×2 GST-clad DCs achieve <1 dB IL and non-volatile switching enabled by substantial Δn, offering zero static power and ns–100 ns event operation useful for FPGA-like photonic meshes (Xu et al., 2018).
Magneto-Optic NOCS: Full-duplex bidirectional operation demonstrated via MO phase shifters at 58–60 ns switching, 7–9 dB IL/unit (~22 dB network-level), and port-count halving via nonreciprocal path separation (Tu et al., 24 Sep 2025).

Device-scale integration leverages CMOS-compatible manufacturing, edge coupling, and multi-layer routing. Key scaling limiters are insertion loss, bond-pad density (for EO), and thermal and magnetic crosstalk. Multi-layer and vertical integration can mitigate these, e.g., through tri-layer shuffle networks or direct CMOS driver stacking (Sun et al., 16 Feb 2025).

4. Cost, Scalability, and Fault Tolerance

OCS cost drivers include port count, coupling density, control electronics, fiber plant, and (in monolithic switches) superlinear scaling with radix.

Switch-centric scaling: Monolithic OCS costs grow as $\propto N^2$ , quickly becoming prohibitive at $N>64$ , motivating modular and distributed approaches. E.g., InfiniteHBD achieves $3.24\times$ lower capex than NVL-72, and $1.59\times$ lower than TPUv4 per-GPU per-Gb/s, with cost per-GPU per-Gb/s: $3.28$ (InfiniteHBD), $5.22$ (TPUv4), $\sim$ 0 (NVL) (Shou et al., 6 Feb 2025).
Arrays of Cheap OCS: Cost scales with number of topologies and resilience modules, not $\sim$ 1; e.g., for 4K GPUs, ACOS is $\sim$ 2 cheaper than packet switch networks, and for small clusters, up to $\sim$ 3 cheaper under relaxed resilience (Amir et al., 19 Feb 2026).
Fault domain and waste: Embedding OCS at the transceiver level reduces the fault-isolation radius ( $\sim$ 4– $\sim$ 5) versus switch-centric approaches where fault domains span 64+ nodes (TPUv4). For $\sim$ 6– $\sim$ 7 node-fault rates, OCSTrx rings achieve $\sim$ 8 waste versus $\sim$ 9 for switch-centric architectures (Shou et al., 6 Feb 2025).

General guidelines for deployment include integrating switch matrices into standard form-factors, pruning to sparse k-hop graphs, containing non-TP traffic inside racks, and capping K to balance failover and complexity.

5. Applications in Datacenter, HPC, and ML Fabrics

OCSes are integral to architectures for AI/ML model training, HPC, backbone/metro transport, and hybrid DCNs:

LLM Training and Parallel ML: High-bandwidth domains (HBDs) for multi-dimensional parallelism (TP, DP, EP) rely on OCS-enabled rings or expander topologies. InfiniteHBD with OCSTrx transceivers achieves $N^2$ 0 improvement in Model FLOPs Utilization and supports >2,800 GPUs at full utilization under 5% node-faults, outperforming NVL and TPU-centric rings (Shou et al., 6 Feb 2025).
Datacenter Interconnect: Google’s TPU v4 relies on OCS to realize 3D, twisted tori dynamically, providing both per-job topology flexibility and strong slice isolation; OCS hardware accounts for <5% system capex and <3% power, and enables system performance/Watt 2.7× that of prior ASIC generations (Jouppi et al., 2023).
Metro/Backbone and WANs: Modular, self-routing OXCs are suitable for 40–160 port metro/core nodes, with capacity for scaled wavelength multiplexing and incremental upgrades (Ye et al., 2020).
Hybrid Packet/OCS Control: Algorithms for robust topology engineering (COUDER) and co-scheduling (Spectra), combined with open SDN controllers, automate infrequent topological reconfiguration to absorb 90+% of workload changes, achieving 20% higher throughput and 32% lower hop-count than static topologies, with sub-1 s reconfiguration latency in field tests (Teh et al., 2020, Anazawa et al., 28 Jan 2025, Liang et al., 7 Mar 2026).

6. Switching Dynamics, Limits, and Future Prospects

Fundamental switching speed limits, integration technologies, and emerging device classes define future potential:

Reconfiguration Dynamics: Conventional MEMS and TO SiPh OCSes are limited to μs–ms, sufficient for coarse ToE but not packet-level dynamic allocation. OCSes based on EO microdisks, SOA-gated microcombs, and MO phase shifters achieve ns or sub-ns reconfiguration, enabling multiplexing in the time domain and near-packet-granularity selection (Sun et al., 16 Feb 2025, Raja et al., 2020, Tu et al., 24 Sep 2025).
Integration Challenges: Scale is limited by cumulative insertion loss, device yield, and electrical interconnect density (especially for EO and PCM meshes). 3D-integration, low-loss stacking, and advanced materials (LiNbO₃ thin films, Ce:YIG) are active research directions (Sun et al., 16 Feb 2025, Tu et al., 24 Sep 2025).
Nonreciprocity and Functionality: The emergence of NOCS (magneto-optic Benes) architectures introduces physical port-count halving with simultaneous bidirectional full-duplex switching at tens of ns reconfiguration (Tu et al., 24 Sep 2025). Heterogeneous integration efforts pair SiPh, III–V E-O, MO, and PCM elements in dense switch-fabrics.

Ongoing work investigates dynamic time-slicing, multi-wavelength control, in-fabric packet switching, and nonblocking unitary mesh architectures for neural, quantum, and reconfigurable photonic computing (Luo et al., 2024, Xu et al., 2018).

References:

(Shou et al., 6 Feb 2025, Ye et al., 2020, Sun et al., 16 Feb 2025, Liang et al., 7 Mar 2026, Takano et al., 2024, Jouppi et al., 2023, Urata et al., 2022, Amir et al., 19 Feb 2026, Teh et al., 2020, Xu et al., 2018, Anazawa et al., 28 Jan 2025, Raja et al., 2020, Luo et al., 2024, Tu et al., 24 Sep 2025)