Hybrid CMOS–Organic Systems

• Hybrid CMOS–Organic Systems are synthetic neuromorphic platforms that integrate CMOS circuits with organic semiconductors to enable adaptive computation and localized processing.
• They utilize nanoparticle engineering and surface functionalization to achieve memristive synaptic functions, including biologically inspired spike-timing-dependent plasticity.
• These systems promote energy-efficient spiking neural networks with tunable synaptic behavior, enhanced scalability, and robustness against device variability.

Hybrid CMOS–organic systems are synthetic neuromorphic platforms that interface CMOS-based electronic circuits with organic semiconductor devices to achieve biologically inspired adaptive computation. A prominent instantiation utilizes the Nanoparticle-Organic Memory Field-Effect Transistor (NOMFET) to natively realize memristive synaptic functions, including spike-timing-dependent plasticity (STDP), in conjunction with standard CMOS testbeds. The hybrid approach leverages organic molecular charge-trapping physics, nanoparticle engineering, and system-level CMOS integration to enable localized, autonomous learning mechanisms and enhanced scalability for spiking neural networks (SNNs) (Alibart et al., 2011).

1. Device Architecture and Materials

The canonical hybrid CMOS–organic synapstor device is structured around the NOMFET, whose material stack is designed for both charge transport and nanoelectronic memory functions. The typical geometry includes a highly doped p⁺⁺–Si back gate with 200 nm thermal SiO₂, further functionalized by an APTMS silane monolayer. Gold nanoparticles (NPs) of 20 nm diameter, stabilized by citrate, self-assemble on the functionalized dielectric, capped with 1,8-octanedithiol to both fix spacing from the organic semiconductor and establish tunnel barriers that modulate charging dynamics. A 35–50 nm pentacene layer, evaporated at 0.1 Å/s, serves as the active organic semiconductor. Source/drain electrodes comprise 20 nm Ti/200 nm Au structured by optical lithography, with aminoethanethiol surface functionalization on the metal to mitigate NP adhesion.

These devices are typically fabricated with channel dimensions of length 5 µm and width 1 000 µm to maximize drain current at pentacene mobility around μ ≈ 10⁻³ cm²/V·s, anticipatable to surpass 1 cm²/V·s with advanced OSCs. All interfaces and materials are compatible with low-temperature, solution-based processing, facilitating integration with standard CMOS platforms and future scaling through advanced gate dielectrics and higher-mobility semiconductors (Alibart et al., 2011).

2. Fabrication Process Flow

Production of hybrid CMOS–organic synapstors follows sequential surface chemistry and microfabrication steps:

1. Substrate cleaning: sequential treatments (chloroform sonication, piranha etch, UV/ozone).
2. Source/drain patterning: optical lithography, e-beam evaporation of Ti/Au, lift-off.
3. Aminoethanethiol SAM deposition on Au pads to abate NP adhesion.
4. SiO₂ silanization: APTMS treatment in hot toluene for monolayer formation.
5. NP self-assembly: overnight immersion in citrate-stabilized gold NP solution under N₂.
6. NP capping: 1,8-octanedithiol treatment to encapsulate and define NP–OSC spacing.
7. Pentacene organic semiconductor evaporation at controlled low rates.
8. Packaging: devices mounted in TO-cases and wire-bonded for direct interfacing with CMOS test boards (Alibart et al., 2011).

This methodology accommodates low-cost, high-yield room-temperature fabrication, accommodates bio-compatible voltages, and facilities modular integration with CMOS peripheral circuitry for system-level experimentation.

3. Electrical Properties and Memristive Phenomena

The NOMFET operates within Chua’s memristor formalism:

• Drain–source current:

$$I_{\mathrm{DS}}(t) = G(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t)) \cdot V_{\mathrm{DS}}(t)$$

• NP charge kinetics:

$$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$

To first order:

$$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$

$$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$

The device exhibits three distinct regimes based on applied $V_{\mathrm{DS}}$:

• $V_{\mathrm{DS}} < 0$ V: hole tunneling into NPs (charging), decreasing channel conductance
• $0 < V_{\mathrm{DS}} < 15$ V: negligible net charge motion (g ≈ 0)
• $V_{\mathrm{DS}} > 15$ V: field-assisted detrapping, restoring conductance

Experimentally, $\Delta I / I$ versus pulse voltage is well described for $V_{\mathrm{DS}} < 0$:

$$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$0

and for $$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$1:

$$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$2

with $$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$3\,V$$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$4, $$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$5\,V$$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$6, $$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$7 V.

Charge/discharge time constants ($$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$8) are tunable from 1–100 s via NP capping ligand chemistry. This enables optimization of volatile/non-volatile synaptic behavior.

Physical mechanism: NPs at the OSC/dielectric interface trap/detrap holes under external $$\dot{Q}_{\mathrm{NP}}(t) = g(Q_{\mathrm{NP}}(t), V_{\mathrm{DS}}(t))$$9, modulating local electric fields and thus the channel conductivity by screening pentacene carriers (Alibart et al., 2011).

4. Spike-Timing-Dependent Plasticity and Synaptic Coding

NOMFETs natively support autonomous STDP. The mechanism employs superimposed pre- and post-synaptic voltage pulses (triangular or rectangular; ±15 V to ∓30 V for 2 s each), with effective $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$0 engineered so that relative spike timing ($$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$1) governs the ensuing conductance change.

Measured STDP learning windows, defined as $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$2 versus $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$3, display:

• $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$4 (pre before post): net NP detrapping, $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$5 (potentiation)
• $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$6 (post before pre): net NP trapping, $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$7 (depression)
• Window amplitude tunable from –15% to +30% over $$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$8 s by pulse shape and device parameters

Fitted learning rule (triangular pulses):

$$I_{\mathrm{DS}}(t) \approx G_0(V_{\mathrm{DS}}) \cdot (1 - \gamma Q_{\mathrm{NP}}(t)) \cdot V_{\mathrm{DS}}(t)$$9

with $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$0, $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$1 s; $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$2, $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$3 s.

These dynamics replicate the fundamental temporal learning rules observed in biological synapses, with the shape and width of potentiation/depression windows programmable via waveform engineering.

5. Circuit-Level Modeling, CMOS Integration, and System Architecture

A behavioral macro-model for circuit simulation encapsulates the device's nonlinear, history-dependent conductance:

• State variable $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$4 (trapped-charge voltage)
• Coupled evolution:

$$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$5

$$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$6

$$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$7 is a piecewise function of drive voltage, with empirically determined breakpoints (e.g., $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$8 V, $$\Delta I_{\mathrm{DS}} / I_{\mathrm{DS}} \approx -\gamma \Delta Q_{\mathrm{NP}}$$9 V, $V_{\mathrm{DS}}$0 V).

Typical parameters for SPICE-level macros:

• $V_{\mathrm{DS}}$1 V, attenuation factor $V_{\mathrm{DS}}$2
• $V_{\mathrm{DS}}$3 determined via diode model ($V_{\mathrm{DS}}$4 A, $V_{\mathrm{DS}}$5 mV)
• $V_{\mathrm{DS}}$6–5 s; $V_{\mathrm{DS}}$7 V$V_{\mathrm{DS}}$8, $V_{\mathrm{DS}}$9 V$V_{\mathrm{DS}} < 0$0

System integration is realized by mounting NOMFETs in TO-cases, wire-bonded to PCBs, and interfaced with CMOS-based pulse circuitry comprising analog multiplexers (e.g., MAX14752), transimpedance amplifiers (OPA445), ADCs (LTC1856), and digital timing (FPGA) under external PC control. Spike pulses ($V_{\mathrm{DS}} < 0$130 V, 0.1–0.2 Hz) are delivered with controlled timing; $V_{\mathrm{DS}} < 0$2 readout utilizes non-disturbing pulses.

Array-level prospects include sharing global read drivers and local spike drivers across NOMFETs, with CMOS “neurons” generating spikes and memristive weights encoded and updated locally by each device. Variability robustness is inherently enhanced due to coding based on spike timing rather than absolute amplitude (Alibart et al., 2011).

6. Performance Considerations and Practical Integration

The combination of localized, molecular charge-based plasticity with CMOS logic enables several notable design principles:

• Plasticity: Autonomous, device-local implementation of STDP through programmable NP charge trapping.
• Cost and processing: Room-temperature, compatible with low-cost and bio-compatible voltages (scalable to <5 V with high-$V_{\mathrm{DS}} < 0$3 dielectric, improved OSC).
• Energy efficiency: Update energy fundamentally limited by NP charging (fJ–pJ), tunable via NP size/density and OSC properties.
• Speed: Governed by trap/escape time in NP–OSC/tunnel barrier system (1–100 s); prospective acceleration by materials engineering (e.g., ligand length, conjugation, OSC mobility).
• Variability tolerance: Synaptic update relies on $V_{\mathrm{DS}} < 0$4 coding, masking device-to-device variability in static $V_{\mathrm{DS}} < 0$5–$V_{\mathrm{DS}} < 0$6.

Integration barriers include high operating voltages and relatively slow update dynamics. High-$V_{\mathrm{DS}} < 0$7 dielectrics, optimized ligand barriers, and advanced organic semiconductors offer pathways for scaling up speed and reducing power. Dynamic, timing-based coding overcomes static $V_{\mathrm{DS}} < 0$8–$V_{\mathrm{DS}} < 0$9 variability.

7. Significance for Neuromorphic Engineering

Hybrid CMOS–organic synapstors provide a compact, fully memristive building block for SNNs, capable of native learning, scaling, and robust circuit-level integration. The approach is inherently amenable to large-scale arrays due to shared drivers and intrinsic robustness to fabrication-driven variability. Prospective implications include the realization of energy-efficient, all-electronic platforms for spiking computation, biologically inspired classification, and adaptive information processing (Alibart et al., 2011).