Noise Equivalent Field (NEF)

• Noise Equivalent Field (NEF) is a metric that quantifies current-noise efficiency in biopotential recording front-ends by comparing RMS noise to an ideal differential BJT benchmark.
• It is used to benchmark and track performance across various architectures and technology nodes, including capacitive-feedback, direct-conversion, and discrete-time amplifiers.
• Design guidelines focus on optimizing bias current, device sizing, and noise reduction techniques like chopping to achieve lower NEF values and improved front-end performance.

The Noise Efficiency Factor (NEF) is a widely used figure of merit for quantifying the performance of biopotential recording front-ends, particularly in CMOS circuits. It benchmarks the input-referred noise performance of a device against the theoretical minimum noise achievable by an ideal differential bipolar transistor (BJT) stage operating at the same bias current and bandwidth. An NEF value of 1 indicates equivalence to this ideal reference, while higher values denote inferior current-noise efficiency. Designs achieving NEF less than 1—characteristic of recent discrete-time architectures—surpass the BJT benchmark. NEF is instrumental in systematic design comparison and performance tracking across evolving technology nodes and amplifier architectures (Lee, 2023).

1. Mathematical Foundation and Physical Interpretation

The input-referred noise of a low-noise front-end is defined by the root-mean-square (RMS) value: $$v_{n,\mathrm{rms}} = \sqrt{ \int_0^{BW_\mathrm{fe}} S_{v_n}(f) \, df }$$ where $BW_\mathrm{fe}$ is the front-end signal bandwidth, and $S_{v_n}(f)$ is the total noise spectral density (both thermal and flicker contributions).

The NEF is constructed by normalizing $v_{n,\mathrm{rms}}$ to the noise floor of a differential BJT reference amplifier with identical bias current $I_{DD}$ and bandwidth: $$\mathrm{NEF} = v_{n,\mathrm{rms}} \cdot \sqrt{ \frac{ I_{DD} }{ 2\pi k T U_T BW_{\mathrm{fe}} } }$$ Here,

• $k$ is Boltzmann’s constant,
• $T$ is absolute temperature,
• $U_T = kT/q$ is the thermal voltage.

This formulation sets an architecture- and technology-independent minimum noise bound, with NEF quantifying excess noise over optimal current-noise efficiency. The definition is generalizable; single-ended BJT references result in a “single-BJT NEF” that is $\sqrt{2}$ lower than the differential case.

2. Derivation and Formula Construction

The reference BJT stage’s per-Hz noise spectral density is

$S_{v_n, \mathrm{bjt}} = \frac{4kT}{g_m}$

where $g_m = I_C / U_T$. Integrating across the effective noise bandwidth and converting to RMS form yields: $$v_{n,\mathrm{diff\text{-}bjt,tot}} = \sqrt{ \frac{ 2 \pi k T U_T }{ I_C }\,BW_{\mathrm{bjt}} }$$ Equivalence is established by setting $I_C = I_{DD}$ and $BW_{\mathrm{bjt}} = BW_{\mathrm{fe}}$, yielding the normalization in the NEF expression above. The formula denotes that NEF gauges current-normalized noise, decoupled from circuit topology or process technology.

3. Typical NEF Ranges Across Architectures and Technology Nodes

Extensive literature surveys (referenced in (Lee, 2023), Fig. 2) provide the following characteristic NEF values:

Architecture Type	NEF Range	Historical/Process Notes
Capacitive-feedback front-ends	1–10	Dominant from 0.35 µm to 22 nm
Direct-conversion front-ends	1–10	Lower NEF in advanced nodes
Discrete-time/parametric amps	0.2–0.45	Recent research, below unity NEF
Resistive-feedback/open-loop	>10	Higher flicker/thermal noise

Discrete-time amplification has enabled sub-unity NEFs in recent prototypes, while capacitive- and direct-conversion front-ends typically inhabit the 1–10 range. Architectures prone to excess flicker noise or reduced bias current efficiency often exceed NEF = 10.

4. Relationship to Power-Efficiency Factor (PEF) and the Composite Metric |PEF–NEF|

While NEF quantifies current-noise efficiency (ignoring supply voltage), the power efficiency factor (PEF) incorporates $V_{DD}$ and benchmarks power-noise efficiency: $$\mathrm{PEF} = \mathrm{NEF}^2\,V_{DD} = \frac{ v_{n,\mathrm{rms}}^2 \cdot 2 I_{DD} V_{DD} }{ \pi k T U_T BW_{\mathrm{fe}} }$$ or equivalently,

$$\mathrm{PEF} = \frac{ v_{n,\mathrm{rms}}^2 \cdot P_\mathrm{tot} }{ \pi k T U_T BW_{\mathrm{fe}} }$$

where $P_\mathrm{tot} = I_{DD} V_{DD}$.

To evaluate trade-offs, the difference $|\,\mathrm{PEF} - \mathrm{NEF}\,|$ is introduced:

• $\mathrm{PEF} > \mathrm{NEF}$: power-noise efficiency lags current-noise efficiency,
• $\mathrm{PEF} < \mathrm{NEF}$: current-noise is the limiting factor,
• Minimizing $|\,\mathrm{PEF} - \mathrm{NEF}\,|$ signals balanced design.

A single front-end may excel in NEF (for instance, by lowering flicker noise via chopping) while suffering in PEF if extra power is consumed elsewhere (e.g., in clock circuits or higher $V_{DD}$).

5. Performance Mapping and Surveyed Trends

A performance mapping method systematically compares design parameters—technology node, NEF, PEF, $|\mathrm{PEF}-\mathrm{NEF}|$, and $V_{DD}$—by plotting each amplifier as a polyline across these dimensions. Individual implementations are distinguished versus architecture averages (Lee, 2023), Figs. 4–5.

Notable empirical trends include:

• CFFEs span a wide node range, cluster at NEF ≈ 1–10, PEF ≈ 1–100, and can approach $|\,\mathrm{PEF} - \mathrm{NEF}\,| \approx 0.5$.
• DCFEs access lower NEF and PEF in advanced nodes.
• Discrete-time amplifiers can realize NEF < 1, PEF < 0.5 V·NEF², though few such circuits exist.
• Reduced supply voltages ($V_{DD}$) favor PEF, unless this reduction increases noise or clocking artifacts, which can compromise NEF and elevate $|\,\mathrm{PEF} - \mathrm{NEF}\,|$.

6. Design Guidelines for Optimizing NEF

Effective NEF minimization is achieved through a systematic approach:

• Maximize input transconductance ($g_m$) by biasing the input transistor at higher current or using parallel devices, but regulate total bias ($I_{DD}$) to avoid diminishing returns due to square-root scaling in NEF.
• Use larger input device area to suppress flicker noise, weighing junction capacitance against required bandwidth.
• In multi-stage front-end chains (e.g., MMRS architectures), allocate the majority of current and lowest $V_{DD}$ to the first gain stage ($G_1$), enabling low-power operation in downstream elements.
• Deploy chopping or auto-zero to attenuate flicker noise—though clock feedthrough and input impedance effects must be managed via careful filtering and added capacitance.
• In direct-conversion ($\Sigma\Delta$) front-ends, partition supplies: operate the analog loop at higher $V_{AVDD}$ for analog performance and run digital quantizers/DACs at lower $V_{DVDD}$ to reduce PEF, with total NEF determined primarily by the analog noise contributions.
• Transitioning to advanced process nodes provides only marginal improvements in thermal noise per watt, while flicker noise may worsen; thus, meticulous device sizing and layout become dominant concerns over pure process scaling.

Adherence to these guidelines—centered on maximizing front-end transconductance, differential architecture, capacitive feedback, noise-reduction techniques, and judicious supply partitioning—enables systematic advancement toward unity or sub-unity NEF while maintaining competitive power efficiency (Lee, 2023).