NMPC on Microcontrollers

• NMPC on Microcontrollers (NMPCM) is a control strategy that implements nonlinear model predictive control on resource-constrained hardware, exemplified by quadrotor applications on Teensy 4.1.
• It employs diverse solver architectures such as full online NMPC, matrix-free methods, and time-certified box-QP formulations to satisfy real-time constraints with limited memory and processing power.
• Techniques like warm-starting, RTI-based solvers, and learned neural approximations are used to optimize performance, ensure predictable execution, and balance the trade-offs between optimal control and hardware limitations.

Searching arXiv for papers on NMPC on microcontrollers and embedded implementations to ground the encyclopedia entry. In current arXiv usage, “NMPCM” denotes “Nonlinear Model Predictive Control on Resource-Constrained Microcontrollers,” exemplified by direct deployment of full nonlinear MPC for quadrotor UAVs on a Teensy 4.1 microcontroller (Nguyen et al., 28 Jul 2025). The broader embedded-control literature shows that the topic also includes adjacent strategies for obtaining NMPC-grade behavior under strict RAM, flash, arithmetic, and sampling-time constraints: real-time iteration schemes with specialized QP cores, matrix-free first-order methods, time-certified box-constrained formulations, multirate discretizations, and neural surrogates trained to imitate an NMPC feedback law (Paluch et al., 2024).

1. Scope and technical landscape

NMPC on microcontrollers addresses the tension between the algorithmic structure of receding-horizon nonlinear optimal control and the resource envelope of MCU-class hardware. The defining constraints in the cited literature are limited RAM and flash, fixed sampling deadlines, modest clock rates, static memory allocation, and a preference for simple arithmetic kernels such as box projections, dense matrix-vector products, or fixed-point multilayer perceptrons.

The contemporary literature separates the field into several recurring implementation patterns.

Mode	Representative papers	Embedded mechanism
Full online NMPC	(Nguyen et al., 28 Jul 2025)	ACADO code generation, RTI, qpOASES, RK4, MCU deployment
Matrix-free embedded NMPC	(Stella et al., 2017, Small et al., 2018, Knyazev et al., 2015)	PANOC or continuation/Krylov updates, no generic QP solve
Time-certified approximations	(Wu et al., 2024, Wu et al., 2024)	Box-QP structure, exact iteration count, explicit flop bounds
Learned controller or model	(Paluch et al., 2024, Gordon et al., 2023, Pham et al., 2022)	Offline NMPC supervision, compact DNN/MLP inference online
Convex MPC kernels for RTI subproblems	(Nguyen et al., 2023, Wu et al., 20 Jan 2026)	ADMM, Riccati structure, construction-free or low-memory QP updates

This suggests a wider operational meaning of NMPCM in current research: not only solving the original nonlinear program online, but redesigning the model, discretization, solver, or control law representation so that receding-horizon control remains compatible with microcontroller-class execution.

2. Full nonlinear optimization directly on microcontrollers

The most literal form of NMPCM is the direct execution of full nonlinear MPC on an MCU. The paper “NMPCM: Nonlinear Model Predictive Control on Resource-Constrained Microcontrollers” (Nguyen et al., 28 Jul 2025) formulates a quadrotor OCP with a 12-state rigid-body model,

$$\mathbf{x}(t)= \begin{bmatrix} p & q & r & \phi & \theta & \psi & \dot p & \dot q & \dot r & \dot\phi & \dot\theta & \dot\psi \end{bmatrix}^T,$$

control inputs

$$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$

and box constraints

$$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$

The continuous-time cost is the standard tracking form

$$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$

with explicit state and input bounds in the generic formulation.

The implementation uses ACADO code generation, multiple shooting, Gauss–Newton SQP, real-time iteration, qpOASES, and RK4 integration, together with a cascaded PID controller that provides warm-start references for both $\mathbf{x}^{\mathrm r}$ and $\mathbf{u}^{\mathrm r}$ (Nguyen et al., 28 Jul 2025). This warm start is not peripheral: it supplies a physically meaningful nonzero equilibrium thrust and improves active-set reuse on the embedded target.

The target MCU is the Teensy 4.1, with an ARM Cortex-M7 at 600 MHz, 7.75 MB flash, 512 kB RAM1 plus 512 kB RAM2, and 32-bit floating-point support; the implementation constrains itself to 512 kB RAM1 for NMPC variables and code (Nguyen et al., 28 Jul 2025). For integrator step $=5$, the horizon length can be increased up to $N=18$; beyond that, the MCU runs out of memory or fails to solve the optimization problem reliably. With $N=10$, memory consumption is almost constant as integrator step increases, whereas solution time grows with the number of RK4 substeps.

The same paper reports that, in desktop simulation, ACADO-based NMPCM can run at up to 1 kHz, while the compared CasADi-based NMPC reaches only about 30 Hz for similar settings and fails to track properly when the horizon length exceeds 16 (Nguyen et al., 28 Jul 2025). In point-to-point quadrotor simulation, the reported quantitative benchmark gives for NMPCM: settling time $8.612$ s, overshoot $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$0, $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$1, ITAE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$2, IAE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$3, ISE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$4, and ITSE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$5, with better overall metrics than the compared NMPC (ACADO), NMPC (CasADi), cascaded PID, and MPCC configurations (Nguyen et al., 28 Jul 2025).

Real-world experiments on several quadrotor frames show the same architectural point: full nonlinear MPC can be colocated with sensing, estimation, and actuation on the same MCU. For roll $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$6, the reported experimental error measures improve from PID values ISE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$7, ITSE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$8, IAE $$\mathbf{u}(t)= \begin{bmatrix} U_1 & U_2 & U_3 & U_4 \end{bmatrix}^T,$$9, ITAE $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$0 to NMPCM values ISE $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$1, ITSE $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$2, IAE $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$3, ITAE $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$4 (Nguyen et al., 28 Jul 2025). In the context of NMPCM, this is the canonical “full online solve” reference point.

3. Embedded solver architectures and computational kernels

A second major strand of the literature does not begin from a particular plant, but from solver structure. “A Simple and Efficient Algorithm for Nonlinear Model Predictive Control” (Stella et al., 2017) introduces PANOC as a line-search method on the forward-backward envelope for problems of the form

$$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$5

where $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$6 is a smooth single-shooting cost and $$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$7 is a prox-friendly nonsmooth term encoding input constraints. PANOC uses the fixed-point residual

$$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$8

L-BFGS directions, no Hessian evaluation, and no inner QP iterations. The paper explicitly positions PANOC as having low memory requirements and a simple implementation particularly suited for embedded NMPC (Stella et al., 2017).

That algorithmic claim is instantiated in “Aerial navigation in obstructed environments with embedded nonlinear model predictive control” (Small et al., 2018), where a C89 implementation of PANOC solves a single-shooting NMPC problem for a quadrotor MAV at 20 Hz onboard a lab-scale platform. The model is a high-level position controller with state

$$U_1 \in [17.5,25.0]\ \text{N},\qquad U_2,U_3,U_4 \in [-0.1,0.1]\ \text{Nm}.$$9

and inputs

$$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$0

with obstacle avoidance handled by smooth penalties

$$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$1

The implementation uses a 50 ms sampling time, horizon $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$2, a maximum of 200 PANOC iterations, and static memory. Reported performance includes average per-iteration time of $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$3–$$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$4 and $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$5–$$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$6 CPU usage of a single Intel Atom core while running at 20 Hz (Small et al., 2018). The paper also notes that the operations required are evaluations of $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$7, $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$8, projections onto box constraints, and small-memory L-BFGS recursions, which directly matches MCU-friendly arithmetic.

A related matrix-free line derives from continuation NMPC. “Preconditioned Continuation Model Predictive Control” (Knyazev et al., 2015) formulates the online step as the solution of a Jacobian-free linear system $$\big\|\mathbf{x}(t+T)-\mathbf{x}^{\mathrm r}(t+T)\big\|_R^2 +\int_t^{t+T} \left( \big\|\mathbf{x}(\tau)-\mathbf{x}^{\mathrm r}(\tau)\big\|_P^2 + \big\|\mathbf{u}(\tau)-\mathbf{u}^{\mathrm r}(\tau)\big\|_Q^2 \right)d\tau,$$9, where each Krylov iteration requires one evaluation of the nonlinear KKT residual $\mathbf{x}^{\mathrm r}$0, i.e. one forward sweep and one backward sweep over the prediction horizon. The paper’s central embedded point is not the continuation formulation alone, but the preconditioning and Krylov choices: preconditioning reduces required GMRES iterations from about 10 to about 1–2 in the reported setup, and MINRES requires $\mathbf{x}^{\mathrm r}$1 vectors whereas unrestarted GMRES requires $\mathbf{x}^{\mathrm r}$2 vectors (Knyazev et al., 2015). That memory statement is directly relevant on MCU targets where Krylov basis storage is a first-order constraint.

Not all relevant computational kernels solve a nonlinear program directly. “TinyMPC: Model-Predictive Control on Resource-Constrained Microcontrollers” (Nguyen et al., 2023) solves convex linear MPC QPs rather than full NMPC, but its role in NMPCM is explicit: any SQP or RTI NMPC scheme relies on solving a QP at each iteration, and TinyMPC provides a low-memory ADMM core exploiting LQR/Riccati structure. On a Teensy 4.1 it is reported to be roughly $\mathbf{x}^{\mathrm r}$3–$\mathbf{x}^{\mathrm r}$4 faster per iteration than OSQP; on a Crazyflie 2.1 with Cortex-M4F at 168 MHz, 192 kB SRAM, and 1 MB flash, TinyMPC fits where OSQP does not, and runs onboard at 500 Hz with $\mathbf{x}^{\mathrm r}$5 and at 100 Hz with $\mathbf{x}^{\mathrm r}$6 for obstacle-constrained flight, typically converging in at most 7 ADMM iterations (Nguyen et al., 2023).

The same “linearized-subproblem kernel” viewpoint motivates “$\mathbf{x}^{\mathrm r}$7MPC: A Parallel-in-horizon and Construction-free NMPC Solver” (Wu et al., 20 Jan 2026). That paper targets the linear time-varying MPC problems arising from RTI or online-linearized NMPC, but eliminates explicit MPC-to-QP construction. Using a velocity-based augmented state and ADMM, it achieves per-stage closed-form updates and horizon-wise parallel execution. For embedded use, the main consequence is that the algorithm works directly with $\mathbf{x}^{\mathrm r}$8 and convex projections, rather than assembling large condensed matrices (Wu et al., 20 Jan 2026). The paper therefore treats construction-free ADMM as a code-simplicity and memory-footprint strategy for embedded NMPC pipelines.

4. Time-certified and execution-predictable formulations

A distinct line of work makes worst-case execution time a primary design variable. The common mechanism is to replace general nonlinear-program timing by a fixed-dimension box-QP or lifted linear MPC problem whose iteration count is known a priori.

“Time-certified Input-constrained NMPC via Koopman Operator” (Wu et al., 2024) considers an input-constrained NMPC problem, lifts the nonlinear dynamics to a linear predictor

$\mathbf{x}^{\mathrm r}$9

and condenses the resulting Koopman-based MPC problem into

$\mathbf{u}^{\mathrm r}$0

The solver is a feasible path-following full-Newton IPM with exact iteration count

$\mathbf{u}^{\mathrm r}$1

depending only on $\mathbf{u}^{\mathrm r}$2 and the target duality-gap tolerance $\mathbf{u}^{\mathrm r}$3 (Wu et al., 2024). In the Korteweg–de Vries example, the lifted dimension is $\mathbf{u}^{\mathrm r}$4, the condensed box-QP dimension is $\mathbf{u}^{\mathrm r}$5, $\mathbf{u}^{\mathrm r}$6, and the exact iteration count is $\mathbf{u}^{\mathrm r}$7. The paper reports approximately $\mathbf{u}^{\mathrm r}$8 FLOPs per MPC step, an observed maximum solving time of about $\mathbf{u}^{\mathrm r}$9 s, and satisfaction of the sampling time $=5$0 s (Wu et al., 2024). The same paper is explicit that this certificate holds for input constraints only; there are no state constraints in the certified formulation.

“An Execution-time-certified Riccati-based IPM Algorithm for RTI-based Input-constrained NMPC” (Wu et al., 2024) keeps the nonlinear model but inserts certification at the RTI-QP level. After one-step linearization and input scaling, the feedback-phase subproblem becomes a box-constrained QP in the stacked control increments. The IPM again uses a fixed number of iterations, but solves each Newton system via a factorized Riccati recursion whose cost scales linearly with horizon length $=5$1. The paper provides explicit flop counts for both preparation and feedback phases. In the Lorenz example with $=5$2, $=5$3, $=5$4, $=5$5, and $=5$6, the QP dimension is $=5$7, the exact number of IPM iterations is $=5$8, and the total cost per sample is about $=5$9 FLOPs, corresponding to approximately $N=18$0 ms on a 1 GFLOP/s processor (Wu et al., 2024).

These papers clarify an important boundary condition in the field. Time-certified NMPCM is currently strongest where the online problem can be reduced to fixed-dimension linear algebra with box input constraints. This yields rigorous timing guarantees, but it also narrows the admissible constraint class.

5. Learned surrogates and learned prediction models

Neural methods enter the NMPCM literature in two technically distinct ways: as controller surrogates that replace the online optimizer, and as learned models retained inside the NMPC loop.

“Hardware Neural Control of CartPole and F1TENTH Race Car” (Paluch et al., 2024) is the clearest controller-distillation example. It formulates an NMPC problem offline, generates state–action supervision from the NMPC teacher, trains a small MLP neural controller $N=18$1, and deploys that controller in quantized fixed point on a low-cost FPGA SoC. For the cart-pole task, the reported network is an MLP $N=18$2 with 1,345 parameters and latency $N=18$3 at 25 MHz; for F1TENTH it is $N=18$4 with 16,778 parameters, about $N=18$5 pruned to zero, and latency $N=18$6 (Paluch et al., 2024). The same paper explicitly maps these networks to microcontroller-scale budgets: the cart-pole controller uses about $N=18$7 kB of weights at 2 bytes per parameter and fewer than 200 bytes of activations; the F1TENTH controller uses about $N=18$8 kB of weights and about 1 kB of activations. The reported MAC counts are about $N=18$9k and $N=10$0k per inference, respectively, and the paper argues that hundreds of Hz, and in the smaller case kHz, are realistic on MCUs. In experiments, the neural controllers match NMPC in simulation and outperform it in reality because the faster control rate compensates for approximation error (Paluch et al., 2024). The same source also states that no formal proofs of stability are provided; robustness and safety are evaluated empirically.

The second route keeps optimization online but replaces the plant model by a learned model. “Introducing a Deep Neural Network-based Model Predictive Control Framework for Rapid Controller Implementation” (Gordon et al., 2023) develops a DNN-based nonlinear MPC for HCCI combustion control using a compact LSTM-plus-fully-connected model with 2,260 learnable parameters. The DNN is cast into a discrete-time state-space model with LSTM internal state

$N=10$1

and is embedded into an acados-based NMPC running on an ARM Cortex-A72. The paper reports validation errors under $N=10$2 for all outputs and average optimization time $N=10$3 ms per cycle, comfortably below the available 22 ms budget at 1500 rpm (Gordon et al., 2023). It also explicitly notes that the Cortex-A72 platform is more powerful than a typical automotive or MCU-class target, so the result is better interpreted as an embedded-CPU benchmark than a direct microcontroller deployment.

A third learned-control pattern appears in “Investigation of fast-NMPC and deep learning approach in fixed-point-based hierarchical control” (Pham et al., 2022). There, a local NMPC problem is first accelerated by a truncated fast-gradient method with fixed iteration budget $N=10$4 and restart period $N=10$5, yielding $N=10$6 relative to an Ipopt baseline at maximum computation time $N=10$7 s versus $N=10$8 s (Pham et al., 2022). The most demanding subsystem is then replaced by a small feedforward neural network; this allows the control updating period to be reduced from $N=10$9 s to $8.612$0 s and improves closed-loop performance in the cryogenic refrigerator study (Pham et al., 2022). In the language of NMPCM, this is a fixed-point and deterministic-runtime answer to the same question addressed by neural controller distillation.

6. Design trade-offs, limitations, and current research directions

A recurring misconception is that NMPCM must mean full online solution of the original nonlinear program on a bare-metal MCU. The literature is broader. It includes direct full nonlinear solves on Cortex-M7-class hardware (Nguyen et al., 28 Jul 2025), box-QP reductions with certified timing (Wu et al., 2024), RTI-based certified Riccati IPM (Wu et al., 2024), matrix-free first-order or Krylov methods (Stella et al., 2017, Knyazev et al., 2015), and offline-learned surrogates that approximate an NMPC policy in fixed point (Paluch et al., 2024). That diversity is not merely taxonomic; it reflects genuinely different trade-offs between optimality, certification, implementation complexity, and hardware envelope.

Another persistent trade-off is between fidelity of the prediction model and problem size. “A Multirate Variational Approach to Nonlinear MPC” (Lishkova et al., 2021) addresses this at the discretization level by combining multirate variational integrators with tube-based successive linearization. In the Fermi–Pasta–Ulam example, increasing the multirate factor from $8.612$1 to $8.612$2 reduced total CPU time for the reported Algorithm 1 from about $8.612$3 s to about $8.612$4 s, while preserving the robust tube-based NMPC framework (Lishkova et al., 2021). The same paper also shows better conservation behavior for the variational discretization than a Forward Euler scheme in the compared mechanical example. This suggests that, for MCU-scale NMPC, reducing the number of optimization nodes by multirate structure can be as consequential as changing the solver.

The limits of current timing guarantees are equally clear. Both certified lines cited above are explicit that the strongest results are obtained for input-constrained problems with box structure; the state-constrained case is not covered by the same exact complexity arguments (Wu et al., 2024, Wu et al., 2024). Conversely, the most flexible embedded formulations—PANOC with soft obstacle penalties, neural surrogates, or continuation methods—typically give up exact iteration or formal closed-loop certificates (Small et al., 2018, Paluch et al., 2024, Knyazev et al., 2015).

A further point of clarification concerns the status of high-speed convex MPC cores. TinyMPC and $8.612$5MPC are not, by themselves, full NMPC solvers; TinyMPC solves convex linear MPC QPs, and $8.612$6MPC targets linear time-varying MPC subproblems arising from RTI or online linearization (Nguyen et al., 2023, Wu et al., 20 Jan 2026). Their relevance to NMPCM is nevertheless direct because RTI, SQP, and many successive-linearization methods reduce online nonlinear control to repeated structured convex subproblems. In that setting, low-memory ADMM, Riccati recursion, and construction-free stage-wise updates become enabling technologies rather than adjacent curiosities.

The field therefore remains defined by a set of coupled design decisions rather than a single canonical algorithm: whether to solve the nonlinear program online or distill it offline; whether to certify time or certify only empirical performance; whether to retain state constraints explicitly or absorb them into soft penalties or tubes; whether to spend resources on model fidelity, multirate structure, or solver acceleration; and whether the target is a Cortex-M-class MCU, a Cortex-A-class embedded CPU, or FPGA-assisted logic. The current literature indicates that all of these choices can produce viable NMPCM systems, but under different assumptions, constraint classes, and guarantees.