MOST: Monolithic Stitched CMOS Sensor

• MOST is a wafer-scale stitched CMOS sensor prototype that validates high-density pixel integration, asynchronous timing readout, and long-distance data transmission for ITS3 upgrades.
• It employs innovative power-domain switching and a novel front-end reverse-bias method to achieve fault isolation and high pixel yield across a 26 cm sensor length.
• The design demonstrates effective hit-driven timing and data transport, though challenges in readout-path jitter remain, guiding future sensor architecture improvements.

MOnolithic Stitched Sensor with Timing (MOST) is a wafer-scale monolithic stitched CMOS pixel sensor prototype developed for the ALICE ITS3 inner-tracker upgrade and for broader CERN R&D on stitched monolithic detectors. Together with the related MOSS device, it was produced to de-risk the final ITS3 sensor concept: three layers of bent, wafer-scale monolithic pixel sensors thinned to $50~\mu\mathrm{m}$ and arranged around the beam pipe. MOST is the timing-oriented and more aggressively integrated member of this pair. Its purpose is to validate very high pixel density, long-distance stitched transmission for power and data, granular power-domain switching for fault tolerance, an alternative reverse-bias scheme applied through the front-end, and an asynchronous readout that preserves hit timing information across a sensor about $26~\mathrm{cm}$ long (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

1. Position in the ALICE ITS3 development program

ITS3 replaces the innermost three layers of the ALICE Inner Tracking System with a bent, ultra-light tracker based on wafer-scale monolithic active pixel sensors. The detector concept relies on sensors fabricated on a 300 mm wafer, thinned to $50~\mu\mathrm{m}$, and bent into cylindrical layers with a material budget of only $0.09\%~X_0$ per layer. In this context, MOST is not a final detector ASIC but a technology demonstrator for the stitched, thin, highly integrated architecture required by ITS3 (Selina et al., 18 Apr 2025).

MOST and MOSS were designed as complementary approaches to the same wafer-scale problem. MOSS is the more conservative structure, with synchronous readout and more segmented externally accessible power domains. MOST instead concentrates several higher-risk design choices into a single prototype: maximum integration density, hit-driven timing-capable readout, and internal power-domain switching. A later overview describes the two chips as complementary design approaches used to evaluate stitched CMOS sensors for the first time in a high-energy-physics experiment, with MOST specifically targeting timing-capable readout and power-gating concepts at wafer scale (Tiltmann, 21 Mar 2026).

This placement within the ITS3 R&D chain is central to interpreting MOST. It was intended to answer whether a full-scale ITS3-style architecture could remain manufacturable, powerable, and temporally informative when extended across stitched centimeter-scale interconnects. In that sense, MOST functions less as a performance-optimized endpoint than as a concentrated validation platform for the subsequent full-size ITS3 prototype sensor, MOSAIX (Sonneveld et al., 22 Jul 2025).

2. Stitched geometry and pixel organization

MOST is a long, narrow stitched sensor assembled from repeated lithographic fields. Stitching allows a sensor to exceed reticle dimensions by joining multiple exposures into a single continuous die, which is essential for ITS3 because the final detector geometry requires uninterrupted wafer-scale active lengths. MOST is described as a sensor about $259~\mathrm{mm}$ long and $2.5~\mathrm{mm}$ wide, built from 10 repeated stitched units (RSUs) connected along the long axis and terminated by end-cap structures (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

Feature	Reported value	Source context
Length	$25.9~\mathrm{cm}$ or about $259~\mathrm{mm}$	MOST over full stitched die
Width	$0.25~\mathrm{cm}$ or about $2.5~\mathrm{mm}$	Narrow wafer-scale strip
RSUs	10	Repeated stitched units
Pixels per RSU	90,112	MOST repeated unit
Total pixels	more than 900,000 pixels	Full sensor
Pixel pitch	$26~\mathrm{cm}$0 or $26~\mathrm{cm}$1; one overview gives $26~\mathrm{cm}$2	Published descriptions

The published descriptions agree on the overall stitched form factor and on the use of 10 RSUs, but they do not report every geometric detail identically. One account specifies $26~\mathrm{cm}$3, more than 900,000 pixels of $26~\mathrm{cm}$4, and a per-RSU submatrix of 352 rows by 64 columns; another overview gives a uniform $26~\mathrm{cm}$5 pitch across the chip. This suggests that the literature is consistent at the architectural level while differing slightly in parameterization or reporting granularity (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

What remains uniform across the descriptions is the design intent: MOST emphasizes the validation of pixel circuitry at maximum density, together with long stitched lines for signal and power transport. The long, thin geometry is therefore not incidental. It directly emulates the uninterrupted active length needed in the bent ITS3 layers.

3. Asynchronous readout and timing-preserving transport

MOST replaces the synchronous, strobed readout of MOSS with an asynchronous, data-driven architecture. It is not strobed and is purely hit-driven: when a pixel fires, the hit information is immediately transferred from the matrix rather than being latched for later frame-based extraction. The readout preserves pixel address, time of arrival, and time over threshold, making MOST the timing-capable counterpart of MOSS within the stitched-sensor program (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

The time-over-threshold encoding is implemented by transmitting the hit information twice: once when the comparator output rises above threshold and again when it falls back to zero. This was described as similar to a previously studied digital pixel test structure. The hit information propagates through the column, the column address is added at the endcap, and hits are then combined through OR logic into one of four current-mode logic outputs. To reduce collisions from neighboring pixels, each column has four transmission lines. The architecture also supports $26~\mathrm{cm}$6 data transmission over a $26~\mathrm{cm}$7 stitched line (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

The design tradeoff is explicit in the literature. Because hit information is streamed directly onto shared column lines, closely spaced hits can collide and become difficult to decode uniquely. A separate overview states that this architecture is not the one foreseen for the final ITS3 chip; rather, it is an R&D vehicle for testing whether timing information survives long-distance stitched transmission (Tiltmann, 21 Mar 2026).

The timing studies are promising but unresolved. A proceeding reports a jitter of $26~\mathrm{cm}$8 on the calibration path of a pulse, while an earlier characterization gives about $26~\mathrm{cm}$9 for the separate calibration chain over the full $50~\mu\mathrm{m}$0 path. By contrast, the readout chain shows about an order of magnitude higher jitter, described elsewhere as roughly 20 times larger, with a linear increase with sensor distance. The authors state explicitly that this behavior is not compatible with a square-root increase from noise and remains under investigation (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

The architectural implication is important. If timing information can indeed be preserved over the full stitched length, a time-to-digital converter would not need to be placed in every pixel or small pixel group; instead, it could be moved to the periphery in future designs. MOST therefore probes not only transport integrity but also a specific scaling strategy for timing-enabled monolithic sensors (Sonneveld et al., 22 Jul 2025).

4. Power distribution, fault isolation, and yield

MOST’s powering architecture is one of its most distinctive features. Instead of relying on many externally separated matrix power regions, it uses global supplies together with programmable local power switches. Published descriptions differ slightly on the top-level supply count: one characterization describes one global analog and digital power domain, while another overview describes two analog power domains and one digital power domain distributed globally across the full chip. In both descriptions, small matrix fractions can be connected or disconnected to isolate faults without sacrificing the full sensor (Selina et al., 18 Apr 2025, Tiltmann, 21 Mar 2026).

The power-gating granularity is described consistently at the group level: 256 pixels per analog group and 352 pixels per digital group. However, the reported total switch counts differ between publications. One proceeding gives analog power gating for 4 rows of 64 pixels per RSU with 2,560 switches and digital gating for 352 pixels in a column per RSU with 3,520 switches, whereas an earlier characterization reports 3,520 analog switches and 2,560 digital switches. What is common to both accounts is the design principle: the global network is kept conservative and robust, while the circuitry behind the switches is pushed to the full density permitted by the process design rules (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

This switch-based architecture targets two problems simultaneously. First, it provides fault isolation: if a short or defect appears in one region, that region can be disconnected. Second, it makes maximum-density circuit design more tolerable from a yield perspective, because defective subregions need not disable the entire wafer-scale die. Measurements support the modular behavior of this scheme. Power consumption rises linearly as digital and analog power gates are turned on sequentially; in another characterization, currents increased smoothly and uniformly as switches were closed, with no sudden jumps and no plateaus (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

The yield results are correspondingly strong on devices that can be powered. One study reports a yield of more than $50~\mu\mathrm{m}$1 on 80 tested RSUs and an average fraction of non-responding pixels of $50~\mu\mathrm{m}$2 per stitched unit. Another, based on four chips corresponding to 40 stitched units, reports 15 non-fully responsive pixels per 90,112 pixels on average, i.e. a pixel yield better than $50~\mu\mathrm{m}$3. The outliers were structured rather than random: one account mentions one outlier among 180 pixels in one stitched unit, likely due to a defect in a shared line in the missing rows; another reports 160 non-fully responsive pixels concentrated in the same 3 or 4 rows of one RSU (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

These high functional yields coexist with a separate problem in powering yield. An early characterization reports a processing issue causing shorts on the global power network in about 30% of chips measured so far. A later mass-testing campaign on 66 full MOST chips reports that 56.1% of MOST chips could not be powered. The observed failures during ramping indicate problems in the global power grid or in the switches themselves (Selina et al., 18 Apr 2025, Tiltmann, 21 Mar 2026).

A common misconception is that MOST’s power gating can rescue any power-related defect. The published data are more restrictive. Power gating can isolate localized pixel-group faults, but it cannot mitigate shorts in the power grid or switch failures, and no tested MOST chip provided a real rescue case in which a defect appeared only after closing a switch. MOST therefore demonstrated the mechanism of power gating clearly, but not a full in-sample repair scenario for the dominant failure mode (Tiltmann, 21 Mar 2026).

5. Front-end-based reverse bias, threshold behavior, and analog response

MOST implements an alternative reverse-bias scheme in which the substrate is tied to analog ground and the reverse bias is created through the front-end input potential rather than by applying a reverse substrate bias. In one description, the analog circuit ground is connected to the substrate and reverse bias is applied by shifting up the potential at the front-end input using a shifting voltage $50~\mu\mathrm{m}$4; another describes the same concept as shifting the lower rail of the front-end upward by $50~\mu\mathrm{m}$5 with respect to global ground, while raising AVDD above the nominal $50~\mu\mathrm{m}$6 to preserve front-end headroom (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

The appeal of this scheme is architectural simplicity. It avoids reverse-bias protection structures and, in a later overview, is explicitly presented as avoiding distribution of negative voltages across the wafer. The tradeoff is increased analog power if the supply must be raised to maintain operating margin (Sonneveld et al., 22 Jul 2025, Tiltmann, 21 Mar 2026).

The measured dependence on $50~\mu\mathrm{m}$7 follows the expected trend. As $50~\mu\mathrm{m}$8 increases, reverse bias increases, sensor capacitance decreases, threshold decreases, threshold spread decreases, and noise decreases. Another characterization states that the threshold and threshold spread behave as expected and that the noise drops rapidly to about 15 electrons or less before saturating at the present operating point. The same set of measurements is presented as evidence that the shifted-rail biasing scheme effectively increases reverse bias across the sensor diode (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

MOST’s operating window is framed against its signal scale. The expected minimum-ionizing-particle signal is $50~\mu\mathrm{m}$9, and the lowest measured threshold is about $0.09\%~X_0$0. Equally important for the power-segmentation concept, when neighboring regions are switched off the threshold variation in active regions remains well below the noise level of $0.09\%~X_0$1. This indicates that local power switching does not significantly perturb adjacent powered areas (Sonneveld et al., 22 Jul 2025).

Laboratory calibration also shows that MOST’s analog response is usable for spectrometric characterization. Using a $0.09\%~X_0$2 source with $0.09\%~X_0$3 and $0.09\%~X_0$4 photons, the reported behavior includes linear response between injected charge and ToT and pixel-to-pixel variation correctable by pixel-by-pixel ToT-versus-charge calibration. For single-pixel clusters, the energy resolution is reported as

$0.09\%~X_0$5

with a measured value of $0.09\%~X_0$6. Hints of silicon fluorescence and an escape peak are also noted (Tiltmann, 21 Mar 2026).

6. Validation status, unresolved issues, and broader significance

MOST validated several of the core design concepts intended for MOSAIX and for the final ITS3 ASIC family. The reported conclusions are that power-domain switching works as intended, long-distance stitched data transmission works over $0.09\%~X_0$7, timing-capable asynchronous readout is functional, the reverse-bias front-end scheme behaves as expected, and high pixel yield is achievable even with dense circuitry (Sonneveld et al., 22 Jul 2025).

The principal unresolved issue is timing quality on the readout path. The asynchronous architecture itself is operational, but the discrepancy between the low-jitter calibration chain and the substantially worse readout-line jitter remains unexplained. The literature therefore separates functional validation from full timing closure: transport of encoded timing information has been demonstrated in part, but detailed timing behavior is still under study (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

A second point of interpretation concerns failure analysis. MOST’s dominant powering losses were observed in the global power grid or switch infrastructure rather than in local matrix blocks. A plausible implication is that at least part of this vulnerability belongs to the broader Engineering Round 1 interconnect environment. In a separate failure-analysis campaign on MOSS, recurrent shorts were localized to the upper copper metal stack, especially regions compatible with $0.09\%~X_0$8, and the foundry later implemented a mitigation strategy. This does not by itself prove an identical defect mechanism in MOST, but it provides a relevant process-level context for the global-power shorts seen across the stitched-sensor program (Eberwein et al., 17 Mar 2026).

MOST also occupies a specific place within monolithic timing research. Its central question is not whether monolithic pixels can ever reach very small intrinsic time resolution, but whether a wafer-scale stitched architecture can preserve timing information while combining high density, long interconnects, and fault-tolerant powering. A broader reference point is provided by a separate monolithic silicon pixel detector without an internal gain layer that achieved $0.09\%~X_0$9 time resolution using a thin fully depleted sensor and very fast low-noise SiGe HBT front-end electronics. That result concerns a different, non-stitched architecture, but it delineates the wider design space into which MOST’s transport-oriented timing studies fit (Zambito et al., 2023).

Taken together with MOSS, MOST established that stitched wafer-scale sensors are a feasible basis for high-energy-physics detectors. Its significance lies in the combination of features it tested simultaneously: maximum-density in-pixel circuitry, fine-grained switch-based fault isolation, hit-driven ToA/ToT-capable readout, and front-end-based reverse bias on a sensor roughly $259~\mathrm{mm}$0 long. The remaining issues are not the basic feasibility of stitching, but the detailed engineering of global power delivery and the final characterization of readout-path timing.