CMOS-Bonded-Array (CBA) Overview
- CMOS-Bonded-Array (CBA) is an architectural family where array elements and peripheral circuits are partitioned into separate tiers and interconnected through bonding, enabling domain-specific optimization.
- It supports diverse applications including DRAM, smartphone image sensors, and x-ray detectors by decoupling sensing, storage, routing, and peripheral functions for improved efficiency.
- The performance of CBA relies on careful control of bonding pitch, routing parasitics, and interface design, with methodologies such as TCAD extraction and SPICE simulation guiding its optimization.
Searching arXiv for papers on CMOS-Bonded-Array and closely related bonded-array architectures. CMOS-Bonded-Array (CBA) denotes an integration pattern in which array elements, peripheral circuitry, or both are partitioned into separate physical units or tiers and then coupled through bonding or structured assembly rather than implemented as a single monolithic planar block. In the cited literature, the acronym is explicit in monolithic 3D DRAM, where stacked cell layers are connected to an overlying CMOS wafer through hybrid bonding (Lee et al., 12 Mar 2026). Closely related architectures appear in wafer-bonded CMOS image sensors, hybrid x-ray detectors formed by indium bump bonds between absorber and readout arrays, non-contiguous commercial CMOS sensor arrays for space telescopes, and fine-grain heterogeneous 3D stacks of specialized active layers (Nahalingam et al., 2023, Griffith et al., 2012, Kautz et al., 28 Aug 2025, Brunion et al., 6 Oct 2025). Across these contexts, the common principle is architectural decoupling: sensing, storage, routing, filtering, and peripheral functions are optimized separately, while overall system behavior is set by the bonding interface, parasitics, mechanical integration, and calibration burden.
1. Terminology and scope
The cited corpus does not use the term uniformly. In (Lee et al., 12 Mar 2026), CBA is a named system-level integration strategy for monolithic 3D DRAM. In (Nahalingam et al., 2023, Griffith et al., 2012), and (Brunion et al., 6 Oct 2025), the underlying idea appears as wafer-bonded stacked CMOS image sensors, indium-bonded hybrid CMOS detectors, and active-tier 3D stacks enabled by hybrid wafer bonding, but without a single cross-domain formal definition. This suggests that CBA is best understood as an architectural family rather than a universally standardized device class.
Earlier CMOS array literature also provides a conceptual precursor. CMOS-based biosensor arrays place sensing, amplification, calibration, A/D conversion, and digital control close to sensor sites, emphasizing high parallelism, miniaturization, low-power compact readout, and integrated calibration and digitization, even though no dedicated CBA bonding architecture is defined there (0710.4678).
| Context | Partitioned structure | Representative technical feature |
|---|---|---|
| Monolithic 3D DRAM | 3D cell layers + CMOS wafer above | BL Selector + Strap with HCB pitch of 0.75 µm (Si) and 0.62 µm (AOS) |
| Smartphone CIS | Pixel/DRAM/logic tiers or photodiode/transistor split | TSV stacking, Cu-Cu hybrid bonding, 4 µm contact pitch |
| X-ray hybrid CMOS detector | Absorber array + ROIC | Indium bump bonds with 36 µm effective pitch |
| Space telescope detector system | Non-contiguous commercial CMOS sensors with gaps | Filter ghosts engineered to fall between detectors |
| Fine-grain 3D CMOS platform | Stack of specialized active tiers | Record hybrid bonding pitch of 400 nm cited |
A recurring misconception is to equate CBA with generic “3D stacking.” The literature is more specific. In the explicit DRAM usage, CBA is a bonded-periphery architecture whose feasibility depends on routing topology, bonding pitch, and sensing margin, not merely on adding vertical layers (Lee et al., 12 Mar 2026). In imaging and detector systems, the decisive issues are often filter orientation, interconnect reliability, or interpixel capacitive coupling rather than density scaling alone (Nahalingam et al., 2023, Griffith et al., 2012, Kautz et al., 28 Aug 2025).
2. Bonded-periphery CBA in monolithic 3D DRAM
In monolithic 3D DRAM, CBA is a system-technology co-optimized architecture in which the memory array is built in stacked 3D cell layers, while the periphery logic, sense amplifiers, row/column drivers, and routing support are moved onto an overlying CMOS wafer through hybrid bonding (Lee et al., 12 Mar 2026). This removes the conventional long lateral routing bottleneck of planar DRAM and makes the bonding interface, rather than the wafer edge, the critical access path to the array. The study explicitly addresses architecture-to-system co-optimization “beyond the mat-level,” with 16 WLs and 8 BLs per strap routed to sense amplifiers and drivers on the CMOS wafer above the array.
The central problem is the simultaneous optimization of routing congestion, hybrid bonding constraints, periphery access, sensing margin, latency, and array efficiency. Four routing options are evaluated: Direct BLSA connection, BL strapping, Core MUX, and BL Selector + Strap. Direct BLSA connection and Core MUX have the lowest delay, but they require HCB pitches of 0.26 µm (Si) and 0.22 µm (AOS), which are described as too restrictive for manufacturable wafer-to-wafer hybrid bonding. Simple BL strapping relaxes pitch but increases bitline parasitic capacitance enough to degrade sensing. The adopted solution is BL Selector + Strap, which isolates unselected BLs and efficiently routes only the selected local group.
The bitline strap architecture is therefore not a minor layout convenience but the enabling mechanism for physical realizability. With BL Selector + Strap, the effective bitline capacitance is reduced to 6.6 fF, with bonding parasitics included, versus 20 fF for D1b. Initial bitline sensing margins rise to 130 mV (Si) and 189 mV (AOS), compared with 54 mV for D1b. The same topology relaxes HCB pitch to 0.75 µm (Si) and 0.62 µm (AOS), which the authors place within the manufacturable window for wafer-to-wafer HCB.
The paper compares Si access transistors with amorphous oxide semiconductor channels and introduces an Indium-Gallium-Oxide selector in the routing path. At the target density of 2.6 Gb/mm², the Si case requires 137 layers with a total height of 9.6 µm, whereas the AOS case requires 87 layers with a total height of 6.9 µm. The selector is reported to achieve @ 2 V with and a near-ideal 60 mV/dec SS, enabling 16-WL / 8-BL multiplexing.
The quantitative system-level claims are unusually strong for an aggressive 3D memory proposal. The optimized design achieves 2.6 Gb/mm², representing roughly 6× density scaling over D1b 2D DRAM. The nominal row cycle time is 21.3 ns for D1b, less than 10.9 ns for the 3D Si case, and less than 10.5 ns for the 3D AOS case. Per-cell write energy is reduced from 15.50 fJ in D1b to 6.26 fJ in 3D Si and 5.38 fJ in 3D AOS; read energy falls from 3.88 fJ to 1.57 fJ and 1.35 fJ, summarized in the abstract as a 60% reduction in read/write energy. Even at 2.6 Gb/mm², the Si case retains a functional margin of 70 mV.
Methodologically, these results are based on TCAD extraction, compact modeling, and SPICE transient simulation rather than a full silicon demonstration. The models unify the storage-node capacitance at fF, incorporate , , , , routing parasitics from straps and bonding, and BL/WL-selector coupling, and extend to mixed-mode TCAD disturbance analysis with floating-body effects and row-hammering under 10k RH toggles and tRC cycles per 64 ms refresh period. In this formulation, CBA is fundamentally a bonded-periphery architecture whose success depends on co-design of cell array, bonding interface, and routing topology rather than on stacking density alone.
3. Bonded-array image-sensor implementations
In smartphone CMOS image sensors, bonded-array practice appears in three principal forms: TSV-based stacked back-illuminated CIS with a DRAM layer, Cu-Cu hybrid bonded stacked BI-CIS, and 2-layer sequential integration separating photodiodes from pixel transistors (Nahalingam et al., 2023). The common motivation is to separate sensing and logic functions vertically so that chip size, readout speed, and pixel-level device optimization can improve without consuming additional X-Y area.
The TSV-based architecture is a 3-layer stack consisting of a pixel layer, a DRAM layer, and a logic layer. The wafers are fabricated separately and then bonded in sequence using through-silicon vias. The middle DRAM and logic layers are connected by the lower TSV stack, while the pixel layer is connected to the DRAM/logic stack by the upper TSV stack. The practical role of the DRAM tier is buffering. The reported pixel-side readout speed is 120 fps, whereas the output-interface speed is 30 fps; this reduces the effective readout bottleneck and mitigates rolling shutter distortion. Reliability data are reported on a 300 mm wafer with 9000 TSV chains and 1260 TSV units used for stress migration testing. After annealing at 175°C for 1000 hours, the resistance shift is less than 2%. Leakage current between TSV and DRAM substrate at 1 V is described as very low with small variation, and TDDB tests at 180 V for 10,000 seconds show considerably less electrical breakdown.
Cu-Cu hybrid bonding is presented as an alternative to TSV-based stacking because it avoids deep silicon etching, keep-out zones, and some footprint penalties. The method combines metal-to-metal Cu connection with dielectric-to-dielectric bonding and is described as providing very fine pitch interconnects and smaller chip size. The reported test vehicle is a 300 mm wafer with 3 million Cu-Cu connections at 4 µm pitch. Resistance before and after 175°C for 1000 hours shows no significant change. A fabricated stacked BI-CIS is reported at 22.5 megapixels with 1 µm × 1 µm pixel size.
The 2-layer sequential integration architecture is distinct in process flow. Photodiodes occupy one layer and pixel transistors another, with the layers built sequentially rather than as separately finished wafers later bonded. This enables independent optimization of photodiodes and transistors. The reported device reaches 12,000 e- full well capacity, 19% higher quantum efficiency at 530 nm, 28% higher conversion gain, and 14% lower random noise. The paper attributes these gains to partial full trench isolation, reduced boron implantation, larger effective photodiode volume, the use of silicon oxide instead of polysilicon in the trench, and sublocal connections that reduce floating diffusion capacitance. Dynamic range is reported to increase as well.
These implementations clarify an important point about CBA in imaging: the vertical split is not solely about interconnect density. It is also a means of separating photodiode, buffering, logic, and transistor optimization domains. In that respect, smartphone CIS provides a mature empirical counterpart to more speculative bonded-array proposals in computing hardware.
4. Hybrid x-ray detectors and bond-geometry control
A distinct bonded-array realization appears in hybrid CMOS x-ray detectors, where a separately fabricated absorber array and readout array are joined by indium bump bonds (Griffith et al., 2012). The absorber performs photon-to-charge conversion through photoelectric absorption, and the ROIC serves as charge-to-voltage converter and signal processor. The paper does not define CBA formally, but it presents a bonded-array architecture in which absorber geometry, readout geometry, and bond pattern can be optimized independently.
The crucial structural feature is a deliberate mismatch between absorber pitch and readout pitch. In the H2RG-122 detector, the readout array pitch is 18 µm, the absorber array pitch is 36 µm, and only one readout circuit line is bonded to each 36 × 36 µm absorber pixel. This gives the readout an effective pitch of 36 µm. By contrast, H1RG devices use 18 µm absorber pitch and 18 µm readout pitch with every readout multiplexer line bump bonded at each pixel site.
The purpose of the wider effective pitch is to suppress interpixel capacitance. IPC is modeled through a pixel-capacitance picture involving , , 0, and neighboring-pixel signals, and operationally characterized through normalized 3×3 event kernels. The detector was measured in a vacuum chamber at about 1 mbar, at 150 K with PID temperature stability of ±0.2 K, and with 15 V bias. A 2Fe source produced Mn K3 at 5.9 keV and Mn K4 at 6.5 keV. For each detector, two datasets of 100 images each were acquired, with about 5.28 s exposure per image and roughly 100,000 x-ray events total.
IPC extraction used a stringent single-event selection procedure: a primary threshold requiring one dominant pixel, a secondary threshold rejecting obvious split events, exclusion of edge regions, an energy cut around the Mn lines, and a standard deviation test on the four adjacent pixels using the 15 read-noise floor as a cutoff. The selected 3×3 events were then averaged and normalized into IPC kernels.
The results show a clear bond-geometry effect. For H1RG detectors at 18 µm pitch, the center pixel retains about 64%–70% of the signal, each adjacent pixel receives about 6%–8%, and each corner pixel about 1%. For the H2RG-122 with 36 µm effective pitch, the center pixel retains 6, adjacent pixels are about 7–8, and corner pixels about 9. In practical terms, about 90.5% of the signal remains in the center pixel, roughly 1.7% spreads into each adjacent pixel, and about 0.7% into each corner pixel. The larger bond spacing therefore lowers adjacent-pixel coupling by roughly a factor of 3–5 relative to the 18 µm devices.
This architecture demonstrates that in bonded arrays, bond geometry itself is a first-order design variable. The significance is not merely lower crosstalk; reduced IPC also implies less charge spreading, fewer multi-pixel events, lower accumulated read noise when summing events, reduced charge loss outside the 3×3 window, and improved energy resolution.
5. Non-contiguous CMOS arrays in space telescopes
In wide-field space instrumentation, a sensor-systems variant of the CBA idea appears as a non-contiguous array of individual commercial CMOS sensors mounted in a common optomechanical structure, with physical gaps between detectors rather than a monolithic focal plane (Kautz et al., 28 Aug 2025). The motivation is practical: lower cost, shorter schedule, modularity, and the possibility of assigning different detector roles such as imaging, guiding, or wavefront sensing. The penalty is optomechanical complexity, which directly amplifies the stray-light and ghosting problem.
Because the array spans a large field of view, each detector sits at a different field angle and therefore sees a different angle of incidence from the incoming chief ray and beam cone. This is critical for interference filters, whose effective transmission band shifts with tilt. The paper therefore states that each individual bandpass filter should be held perpendicular to the incoming beam in order to prevent detector-to-detector variation in central wavelength. Filter placement becomes simultaneously a spectral-performance and stray-light problem.
Axial filter spacing introduces a second coupled constraint. If the filter is too close to the detector, light reflected from the detector can bounce off the top or bottom filter surfaces and return to the same detector as a ghost. If the filter is too high, the same ghost can land on an adjacent detector. The design strategy is to place the optics so that filter ghosts fall between detectors rather than on active sensor areas.
Stray- and scattered-light mitigation is then delegated to local optomechanics. The design places a cylindrical baffle immediately below each filter optic, extending downward toward the detector, together with an extended wall structure to suppress cross-detector scattering. Near the focal region, where light is more concentrated, a two-tier vane structure blocks higher-intensity stray light. Edge treatment is explicitly identified as important: bevels and chamfers can scatter light, knife edges may perform better than rounded edges, and manufacturing constraints may prevent ideal geometries. A central design rule is to minimize added mechanical structures, since more parts imply more scattering opportunities.
The paper further states that first- and second-order stray light path analyses must be conducted for well-focused, high-intensity beams. Relevant glint sources include optics, optomechanical parts, and detector-specific vane structures. Quantification uses point source transmittance, defined as the ratio of a point source’s integrated irradiance at the detector to its incident irradiance at the entrance pupil as a function of angle relative to field center. A lateral scan PST is also used, in which a focused beam is moved across the entrance aperture, here the upper vane opening, to tune vane geometry for low vignetting within the science field and rapid stray-light falloff outside it. A reported design criterion is that with the upper vane toleranced to 100 0m from the outer marginal ray, stray light drops to about 1 very quickly.
The paper also stresses that tolerancing without alignment control is insufficient. Misalignment can introduce both vignetting and new stray-light paths. The effective tolerancing envelope is set by the margin between the outer marginal rays of the science beam and the nearest safe position of baffle or vane edges. In this domain, the bonded-array idea is realized less as semiconductor bonding than as modular detector integration with local filtering and baffling; nevertheless, the same theme persists: modularity and cost advantages are obtained at the price of much stricter control of parasitics, here optical rather than electrical.
6. Generalization to heterogeneous 3D CMOS, and major constraints
The broader extrapolation of CBA appears in the CMOS 2.0 program, which proposes fine-grain heterogeneous 3D stacking of specialized active device layers enabled by 3D wafer bonding and backside processing (Brunion et al., 6 Oct 2025). The platform is described as a stack of active tiers connected through a fine-grain interconnect network, with each device layer tailored to a specific function. The paper cites sub-micron inter-die connectivity and a record hybrid bonding pitch of 400 nm, alongside backside power distribution networks in sub-2 nm nodes.
Architecturally, the framework decomposes digital systems into four functions: Transform, Sample and hold, Store, and Distribute. On that basis it proposes four partitioning schemes: dense logic versus high-drive logic, combinational versus sequencing logic, communication-layer specialization, and memory array versus periphery. The last of these is explicitly analogous to array-under-CMOS thinking. The paper then projects these ideas onto 3D SRAM, cache stacking, vertically integrated L0 memories, 3D compute-in-memory, 3D systolic arrays, and 3D CGRAs with reconfigurable vertical interconnects.
This generalization helps clarify what CBA is not. It is not merely a packaging option, and it is not exhausted by memory or sensor applications. The cited work treats bonded arrays as a new architectural substrate requiring co-design of FEOL technology, BEOL routing, vertical transitions, pin capacitances, and layer-specific resources. The paper explicitly states that conventional HPWL is insufficient for placement in this regime and argues for cost functions that account for in-plane and out-of-plane route segments and multi-layer parasitics.
At the same time, the literature is explicit about limitations. In the DRAM case, the strongest numerical claims arise from TCAD + SPICE modeling rather than a full silicon demonstration (Lee et al., 12 Mar 2026). In CMOS 2.0, major constraints include thermal and power-density issues, yield loss in multi-layer stacking, test-access bottlenecks, voltage regulation under high current density, runtime variability, hard and soft fault sensitivity, and the requirement for balanced utilization across layers (Brunion et al., 6 Oct 2025). Fine-grain wafer-to-wafer integration is favored for pitch, but it makes yield more challenging. Proposed mitigations include layer specialization for test access, adding hold latches into scan flip-flops, enabling delay-test coverage and state snapshotting, and integrating Silicon Lifecycle Management through dedicated layers for analog sensors, global voltage regulation, BIST and DfT structures, system control logic, and real-time monitoring.
Taken together, these works position CMOS-Bonded-Array as a cross-domain design pattern whose central problem is not simply stacking more layers, but deciding which functions should be separated, how the interfaces should be bonded, and how the resulting parasitics, reliability risks, optical paths, and calibration demands can be controlled. The diversity of implementations—from DRAM to smartphone CIS, x-ray detectors, and space-telescope focal planes—suggests that the most stable meaning of CBA is architectural rather than taxonomic: a bonded or modular array organization in which the interface itself becomes a primary determinant of system performance.