MOSS: Wafer-Scale Stitched Sensor for ALICE ITS3

• MOSS is a monolithic stitched sensor demonstrator that validates wafer-scale CMOS pixel detectors by achieving dimensions far beyond single-reticle size for the ALICE ITS3 upgrade.
• The sensor employs segmented RSUs with distinct pixel matrices, integrated power domains, and a strobe-based readout to address yield, noise, and timing performance in high-energy experiments.
• Extensive characterization demonstrates high detection efficiency, radiation tolerance, and actionable insights, marking a critical transition from process feasibility to engineering for stitched MAPS.

The MOnolithic Stitched Sensor (MOSS) is the first wafer-scale stitched Monolithic Active Pixel Sensor developed as the full-scale validation prototype for the ALICE ITS3 upgrade. It was designed to demonstrate that a monolithic CMOS pixel detector can be fabricated far beyond single-reticle dimensions by lithographic stitching, thinned to $50\ \mu\mathrm{m}$, and operated with detector-grade yield and performance over a length of about $25.9\ \mathrm{cm}$. Within the ITS3 program, MOSS is a technology demonstrator rather than the final detector chip: its role is to validate stitching, large-area power and signal distribution, yield, and pixel-matrix behavior for the ultra-light, bent, cylindrical vertex detector concept adopted by ALICE (Abdelrahman et al., 13 Oct 2025, Bouchhar, 6 Jun 2026).

1. ITS3 context and the rationale for MOSS

ALICE ITS3 replaces the three innermost ITS2 layers during LHC Long Shutdown 3 with a detector based on stitched wafer-scale MAPS in a $65\ \mathrm{nm}$ CMOS imaging technology. The detector concept uses six half-layers of bent silicon, with the innermost layer at $19.0\ \mathrm{mm}$, the outer two at $25.2$ and $31.5\ \mathrm{mm}$, and half-layer length $26.6\ \mathrm{cm}$. The targeted material budget is about $0.09\%\;X_0$ per layer, compared with about $0.36\%\;X_0$ in ITS2, and the reduction is achieved by replacing stave-based assemblies with ultra-thin, bent, self-supporting silicon and air cooling (Abdelrahman et al., 13 Oct 2025, Bouchhar, 6 Jun 2026).

Stitching is essential because the required sensor dimensions exceed the lithographic reticle size. ITS3 therefore adopts a sensor architecture in which repeated reticle-scale design units are electrically connected across stitching boundaries to form a single monolithic die. MOSS was produced in Engineering Run 1 as the first full stitched prototype to validate this concept experimentally. In the development chain described in the ITS3 literature, earlier MLR1 test structures established the viability of the $65\ \mathrm{nm}$ process, MOSS and MOST provided the first $25.9\ \mathrm{cm}$0-class stitched demonstrators, and MOSAIX is the later full-functionality qualification prototype (Buckland, 2023, Sonneveld et al., 22 Jul 2025, Groettvik, 1 Nov 2025).

A recurring misconception is to treat MOSS as the final ITS3 ASIC or to equate stitching with a simple mosaic of small chips. The ITS3 sources are explicit on both points: MOSS is a demonstrator, and stitching denotes a single electrically continuous sensor fabricated across multiple reticle fields, not post-fabrication tiling (Groettvik, 2024, Abdelrahman et al., 13 Oct 2025).

2. Stitched layout, segmentation, and chip organization

MOSS was fabricated in the Tower Partners Semiconductor $25.9\ \mathrm{cm}$1 CMOS imaging process on $25.9\ \mathrm{cm}$2 wafers. The stitched chip measures $25.9\ \mathrm{cm}$3, equivalently $25.9\ \mathrm{cm}$4, and is thinned to $25.9\ \mathrm{cm}$5. One processed wafer contains six MOSS sensors in the central area together with 23 babyMOSS devices (Abdelrahman et al., 13 Oct 2025, Terlizzi, 19 Feb 2025).

The stitched floorplan consists of a Left End-Cap (LEC), ten Repeated Sensor Units (RSUs), and a Right End-Cap (REC). Each RSU is divided into top and bottom half-units, and each half-unit contains four regions with their own pixel matrix, biasing, control, and readout. The full chip therefore contains 20 half-units and 80 regions. The top regions implement $25.9\ \mathrm{cm}$6 matrices with $25.9\ \mathrm{cm}$7 pitch, while the bottom regions implement $25.9\ \mathrm{cm}$8 matrices with $25.9\ \mathrm{cm}$9 pitch. Summed over all ten RSUs, this gives approximately $65\ \mathrm{nm}$0 million pixels (Terlizzi, 19 Feb 2025, Abdelrahman et al., 13 Oct 2025).

This asymmetry between top and bottom halves is deliberate. The larger-pitch top half probes lower integration density and wider spacing in interconnect structures; the smaller-pitch bottom half probes denser layout. In the ER1 program, MOSS was the prototype dedicated to studying yield dependence on in-pixel circuit density, whereas MOST was built to push maximum density and timing-preserving asynchronous readout (Sonneveld et al., 22 Jul 2025, Selina et al., 18 Apr 2025).

Powering and access were also deliberately segmented. MOSS is described as having 20 fully separated power domains, each accessible by separate pads, and each half-unit can operate autonomously through bond pads along the long edge. At the same time, the chip includes a stitched communication backbone routed near the periphery and full-chip power grids routed even above the pixel arrays. The prototype can therefore be exercised both locally, half-unit by half-unit, and through the end-cap path that is relevant for stitched long-distance operation (Selina et al., 18 Apr 2025, Abdelrahman et al., 13 Oct 2025).

3. Pixel architecture, readout model, and circuit operation

MOSS uses a conventional reverse substrate bias: a negative voltage is applied between the substrate and the front-end ground, with $65\ \mathrm{nm}$1 used in the detailed circuit characterization. This is one of the clearest architectural contrasts with MOST, which explored an alternative front-end-mediated reverse-bias scheme (Selina et al., 18 Apr 2025, Abdelrahman et al., 13 Oct 2025).

At pixel level, the MOSS front-end integrates an analogue stage, digital control logic, and a discriminator output latch. The detailed signal chain reported for the standard pixel is: charge collection at the diode, transistor M1 as an input source follower, M2 together with cascode M4 and sink M9/M8 as a folded-cascode amplification stage, feedback through M5, M6, and M7, and discrimination with M10/M11. The operating point is set by region-local 8-bit DACs. Reported nominal values include a main front-end bias current of $65\ \mathrm{nm}$2, a feedback/reset current of $65\ \mathrm{nm}$3, a discriminator current of $65\ \mathrm{nm}$4, a cascode voltage of $65\ \mathrm{nm}$5, and a level-shifting voltage of $65\ \mathrm{nm}$6 (Abdelrahman et al., 13 Oct 2025).

For calibration and scan-based characterization, MOSS provides both analog charge injection and digital pulsing. One explicit relation used in the threshold-scan workflow is

$65\ \mathrm{nm}$7

with $65\ \mathrm{nm}$8 the injected charge, $65\ \mathrm{nm}$9 the injection capacitance, and $19.0\ \mathrm{mm}$0 the pulser amplitude (Terlizzi, 19 Feb 2025).

The readout model is synchronous and strobe-based. A global strobe signal is distributed across the half-unit, and a hit is stored when the strobe overlaps the asserted discriminator output. The discriminator state is sampled into a pixel latch; after a readout command, the locations of hit pixels are extracted sequentially through a priority-encoder-based sparse readout path and the latches are reset. In the broader ER1 comparison, this is the defining distinction from MOST, which immediately transfers hit information upon a hit and preserves timing information through an asynchronous, data-driven architecture (Selina et al., 18 Apr 2025, Tiltmann, 21 Mar 2026).

One of the most consequential findings of the full MOSS characterization was a non-ideal interaction between this readout scheme and the matrix routing. Capacitive coupling between the distributed strobe line and analogue bias lines perturbs the front-end after the falling edge of the strobe. The perturbation develops on the front-end peak-time scale $19.0\ \mathrm{mm}$1, with recovery in about $19.0\ \mathrm{mm}$2, and it distorts both threshold and fake-hit-rate measurements. For characterization, a short strobe length of $19.0\ \mathrm{mm}$3 was used to close the acquisition window before the perturbation became dominant. The next ITS3 design is intended to remove these strobe-bias crossings and to replace strobe-based hit capture with edge-based hit latching (Abdelrahman et al., 13 Oct 2025).

4. Characterization campaigns, yield definitions, and failure analysis

MOSS was not characterized only as a single demonstrator. A large series-testing campaign covered 82 full MOSS chips from 14 wafers, corresponding to 6560 powered and controlled pixel matrices and more than half a billion individually characterized pixels. A separate large-scale powering campaign covered 120 MOSS chips and 1620 half-RSUs, while the dedicated metal-stack fault-analysis study considered a lot of 24 wafers, six MOSS per wafer, with measurements on chips from up to 20 wafers (Abdelrahman et al., 13 Oct 2025, Eberwein et al., 17 Mar 2026, Tiltmann, 21 Mar 2026).

The functional test flow included powering, digital-periphery tests, analogue-periphery checks, pixel-matrix readout verification, and matrix-performance scans. In the full characterization paper, digital readback covered 402 registers per half-unit. In the earlier CERN mass-test campaign, 7680 applicable registers per chip were exercised, DAC linearity was checked, analog and digital pulsing used 25 repeated injections per pixel, threshold scans used 25 pulses per step per pixel over 0–70 DAC units, and fake-hit-rate scans used 100000 readout cycles per region (Terlizzi, 19 Feb 2025, Abdelrahman et al., 13 Oct 2025).

Several yield numbers coexist in the literature because the definition changes with the test stage and with whether prototype-specific failure modes are excluded. Region-level series testing reported an overall yield of about $19.0\ \mathrm{mm}$4, increasing to about $19.0\ \mathrm{mm}$5 when readout-architecture-specific failures were excluded, and to more than $19.0\ \mathrm{mm}$6 when both readout-architecture limitations and powering issues were excluded. In the same campaign, only $19.0\ \mathrm{mm}$7 of regions contained more than $19.0\ \mathrm{mm}$8 faulty pixels, and only $19.0\ \mathrm{mm}$9 of regions failed because too many pixels were noisy or otherwise uncharacterizable (Abdelrahman et al., 13 Oct 2025). A separate cumulative scan campaign reported stage success rates of $25.2$0 for register scan, $25.2$1 for DAC scan, $25.2$2 for digital scan, $25.2$3 for analogue scan, $25.2$4 for threshold scan, and $25.2$5 for fake-hit-rate scan, summarized there as a yield higher than $25.2$6 (Terlizzi, 19 Feb 2025). This suggests that the apparent numerical spread in quoted yield is driven by differing scopes and acceptance definitions rather than by incompatible measurements.

The dominant non-fundamental failure mode was a short mechanism in the customized power grid. The dedicated analysis identified recurrent shorts between power nets, strongly correlated with the top copper layers M7 and M8 of the adapted metal stack. The evidence combined low-voltage impedance scans, slow power ramping, thermal-camera localization, layout correlation, and FIB-SEM/EDS cross-sections showing copper connections consistent with the implicated M7/M8 structures. Across 1620 half-units tested in the power-ramp campaign, $25.2$7 showed no transient high current, $25.2$8 showed transient high current corresponding to a burnt-through short, and $25.2$9 showed persistent high current or hotspots outside operating limits. Among half-units with at least one short, $31.5\ \mathrm{mm}$0 could be operated within specifications after the short was removed by burn-through (Eberwein et al., 17 Mar 2026).

A critical point in the ITS3 literature is that these failures were not attributed to stitching boundaries. Hotspots occurred across the chip area rather than specifically at stitch seams, and the resulting interpretation is that the limiting defect was a BEOL metal-stack issue in a very large stitched die, not a failure of stitching as such (Eberwein et al., 17 Mar 2026, Tiltmann, 21 Mar 2026).

5. Thresholds, noise, calibration, beam performance, and radiation response

Threshold and noise were extracted from pulsed S-curves. For a representative $31.5\ \mathrm{mm}$1-pitch region, the threshold distribution is reported as Gaussian-like with an RMS of about $31.5\ \mathrm{mm}$2 of the mean threshold. Pixel-to-pixel injection-capacitance variation contributes materially to this apparent spread: X-ray-based calibration later measured an average injection capacitance of $31.5\ \mathrm{mm}$3, close to the design value $31.5\ \mathrm{mm}$4, with a pixel-to-pixel RMS spread of about $31.5\ \mathrm{mm}$5. Threshold also has a temperature coefficient of about $31.5\ \mathrm{mm}$6 between $31.5\ \mathrm{mm}$7 and $31.5\ \mathrm{mm}$8 in a non-irradiated sensor (Abdelrahman et al., 13 Oct 2025).

MOSS also established a calibrated time-over-threshold response. A special long-strobe mode allowed ToT extraction, each pixel was calibrated with a straight-line fit, and X-ray measurements with $31.5\ \mathrm{mm}$9, Ti, Pb, and Pd showed linearity from $26.6\ \mathrm{cm}$0 to $26.6\ \mathrm{cm}$1. For the Mn-$26.6\ \mathrm{cm}$2 line, the reported energy resolution was

$26.6\ \mathrm{cm}$3

The corresponding calibration relation stated for the injection capacitor was

$26.6\ \mathrm{cm}$4

These measurements were used to validate charge collection and ToT linearity on the full stitched sensor (Abdelrahman et al., 13 Oct 2025).

In-beam studies used $26.6\ \mathrm{cm}$5 negative hadrons at the CERN PS with a six-plane ALPIDE telescope, DUT temperature $26.6\ \mathrm{cm}$6, and a $26.6\ \mathrm{cm}$7 track-cluster association radius. The intrinsic sensor spatial resolution was obtained by subtracting the telescope term of about $26.6\ \mathrm{cm}$8 in quadrature,

$26.6\ \mathrm{cm}$9

For the non-irradiated $0.09\%\;X_0$0 matrix, the operational threshold window satisfying the ITS3 efficiency and fake-hit-rate requirements was about $0.09\%\;X_0$1 to $0.09\%\;X_0$2, i.e. about $0.09\%\;X_0$3. After irradiation, this operational margin shrank to less than $0.09\%\;X_0$4 (Abdelrahman et al., 13 Oct 2025).

The pitch trade-off was explicit. The $0.09\%\;X_0$5 matrix offered higher efficiency margin, but the $0.09\%\;X_0$6 matrix provided better spatial resolution. At $0.09\%\;X_0$7, highlighted as the lowest threshold still inside the post-irradiation operating window, the $0.09\%\;X_0$8 pitch reached about $0.09\%\;X_0$9, while the $0.36\%\;X_0$0 pitch reached about $0.36\%\;X_0$1. Across threshold ranges summarized in the conclusion, the $0.36\%\;X_0$2 option yielded about $0.36\%\;X_0$3–$0.36\%\;X_0$4, while the $0.36\%\;X_0$5 option yielded about $0.36\%\;X_0$6–$0.36\%\;X_0$7. Increasing the gap in the $0.36\%\;X_0$8 design from $0.36\%\;X_0$9 to $65\ \mathrm{nm}$0 improved spatial resolution by about $65\ \mathrm{nm}$1–$65\ \mathrm{nm}$2 at thresholds below $65\ \mathrm{nm}$3, consistent with increased charge sharing (Abdelrahman et al., 13 Oct 2025).

Radiation studies intentionally exceeded the ITS3 specification. MOSS was characterized after $65\ \mathrm{nm}$4 TID and $65\ \mathrm{nm}$5 NIEL, whereas the required detector tolerance is $65\ \mathrm{nm}$6 and $65\ \mathrm{nm}$7. The reported result is that MOSS still achieved detection efficiency $65\ \mathrm{nm}$8 with fake-hit rate $65\ \mathrm{nm}$9 at the required ITS3 radiation point, although the working margin narrows after irradiation. TID chiefly increased fake-hit rate through transistor degradation; NIEL increased fake-hit rate through leakage current and shot noise and reduced low-threshold cluster size, worsening spatial resolution by up to $25.9\ \mathrm{cm}$00 at low threshold (Abdelrahman et al., 13 Oct 2025, Tiltmann, 21 Mar 2026).

A related but distinct result came from babyMOSS, the one-RSU reduced implementation of the MOSS architecture. Laboratory and test-beam campaigns reported that babyMOSS results were consistent with full MOSS and met ITS3 requirements with detection efficiency $25.9\ \mathrm{cm}$01, fake-hit rate $25.9\ \mathrm{cm}$02 hits per pixel and event, and spatial resolution $25.9\ \mathrm{cm}$03, including after $25.9\ \mathrm{cm}$04 NIEL in the demonstrated beam tests (Sturniolo, 2 Oct 2025, Rignanese, 3 Feb 2026).

6. Reliability, distinction from MOST, and role in the ITS3 roadmap

MOSS also served as a reliability study vehicle. Proton tests at $25.9\ \mathrm{cm}$05 measured SEU cross-sections between $25.9\ \mathrm{cm}$06 and $25.9\ \mathrm{cm}$07 for monitored registers. Heavy-ion testing revealed SEL sensitivity already below $25.9\ \mathrm{cm}$08, with the sensitive sites traced to peripheral blocks and attributed to insufficient well-contact density. The correction was already identified for the next iteration (Abdelrahman et al., 13 Oct 2025).

The distinction between MOSS and the other ITS3 demonstrators is central to the literature:

Prototype	Defining features	Primary role
MOSS	20 pad-accessible power domains, synchronous or strobe-based readout, reverse substrate bias	First full-scale validation of stitched wafer-scale MAPS
MOST	Global power domains with local switches, immediate asynchronous hit transfer, timing-oriented architecture	Study of power gating, long stitched data transmission, and timing information
MOSAIX	$25.9\ \mathrm{cm}$09, 144 independently powered pixel matrices, eight $25.9\ \mathrm{cm}$10 transmitters	Final development step before production and technical qualification

This comparison clarifies another common misconception: MOSS and MOST are not different names for the same chip. They are complementary ER1 prototypes, and MOSAIX is the later qualification device that integrates lessons from both (Selina et al., 18 Apr 2025, Sonneveld et al., 22 Jul 2025, Groettvik, 1 Nov 2025).

Historically, MOSS is significant because it established the first full-scale validation of stitched MAPS for ALICE ITS3 and, in the broader ITS3 narrative, the first practical demonstration that wafer-scale stitched monolithic sensors can support a bent, ultra-light silicon vertex detector for high-energy physics. The strongest result is not that every prototype feature was final, but that the key risks became separated: stitching itself proved feasible; detector performance reached ITS3-relevant efficiency, fake-hit rate, and radiation tolerance; and the dominant remaining issues were identifiable as prototype readout limitations, power-grid metallurgy, end-only powering, high-speed transmission, and peripheral SEL susceptibility. In the ITS3 roadmap, MOSS therefore marks the transition from process feasibility to full-scale stitched-sensor engineering, while MOSAIX carries the concept toward production qualification (Bouchhar, 6 Jun 2026, Menzel, 4 Nov 2025).