Monolithic Active Pixel Sensors

• Monolithic Active pixel Sensor (MAPS) are silicon detectors that combine electronics and radiation-sensitive components on a single CMOS die to offer thin, high-resolution sensors with reduced material budget, fine granularity, and ease of production.
• MAPS use either diffusion-based (conventional) or drift-based (DMAPS/HV-MAPS) charge collection techniques to achieve effective ionization detection, leading to higher radiation tolerance and spatial resolution.
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• Episodes of MAPS development include devevitations in 65 nm CMOS wafer-scale stitching for ultra-thin, large-area detectors, achieving high spatial and temporal resolution, lower material budget, with proposed advancements in silicon-depleted HV-MAPS for energy-resolution like Ion-Specification and Gamma-Ray Detection.

Monolithic active pixel sensors (MAPS) are silicon detectors in which the radiation-sensitive volume, charge-collection structures, analog front end, and, in many implementations, digital readout circuitry are fabricated on the same CMOS die. Unlike hybrid pixel detectors, which connect a separately fabricated sensor and readout ASIC through bump bonds, MAPS eliminate the sensor–ASIC interconnect, enabling reduced material budget, fine granularity, thin detectors, and potentially lower production complexity. Conventional MAPS collect charge mainly by diffusion in a thin epitaxial layer; depleted MAPS (DMAPS) and high-voltage MAPS (HV-MAPS) instead use high-resistivity silicon and reverse bias to collect charge predominantly by drift. The technology has evolved from low-power imaging and vertex-detector devices into large-area, radiation-tolerant tracking sensors with integrated timing, buffering, zero suppression, serialization, and, in specialized developments, energy-loss or gamma-ray spectroscopy.

1. Device concept and operating physics

A MAPS pixel combines a silicon sensing element with active electronics. A traversing charged particle creates electron–hole pairs in the active sensitive volume. The charge is collected by an n-type diode or collection electrode, amplified locally, compared with a threshold, and either digitized, stored, or transmitted as part of a sparse data stream. Typical signal paths are

$$\text{particle passage}\rightarrow\text{ionization charge}\rightarrow\text{charge collection}\rightarrow\text{amplification}\rightarrow\text{threshold discrimination}\rightarrow\text{buffering}\rightarrow\text{readout}.$$

The collected charge produces a voltage excursion whose magnitude depends on the charge and the input capacitance. In qualitative form,

$$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$

so low input capacitance increases the voltage signal and generally improves the equivalent noise charge (ENC) and signal-to-noise ratio (SNR). The absence of bump-bond capacitance is therefore a significant architectural advantage of MAPS (Apadula et al., 2022).

In conventional CMOS imaging MAPS, the sensing medium is commonly a lightly doped p-type epitaxial layer with resistivity near $10~\Omega\cdot\mathrm{cm}$ and thickness of approximately $4\text{--}20~\mu\mathrm{m}$. Only a small region around the collection diode is depleted. Charge generated outside this region reaches the diode mainly by thermal diffusion. For a one-sided junction, the depletion depth scales approximately as

$W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$

where $\rho$ is substrate resistivity and $V_{\mathrm{bias}}$ is reverse bias. Low resistivity therefore produces a shallow depletion region. Diffusion is slower and less deterministic than drift, spreads charge among neighboring pixels, and becomes vulnerable to recombination and trapping after displacement damage.

A minimum-ionizing particle produces approximately $80$ electron–hole pairs per micrometre of silicon. Thus a $10\text{--}15~\mu\mathrm{m}$ active layer provides a signal of roughly $1000\text{--}1200~e^-$, whereas a fully depleted $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$0 sensor is expected to provide approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$1. Conventional MAPS consequently combine small signal, diffusion-dominated collection, charge sharing, and sensitivity to radiation-induced defects. Their radiation tolerance was historically below LHC requirements by factors of approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$2 (Havránek et al., 2014).

In DMAPS, high-resistivity material and reverse bias generate a substantially larger depleted volume. Charge carriers move mainly by electric-field-driven drift. The drift velocity is approximately

$$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$3

where $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$4 is carrier mobility and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$5 is the electric field. Drift reduces collection time and the probability of trapping. It can also reduce charge sharing and increase the seed-pixel signal. The principal architectural trade-off is between large collection electrodes, which provide broad depletion and strong fields but high capacitance, and small collection electrodes, which provide low capacitance and low noise but require carefully engineered lateral depletion.

2. Pixel circuits, signal processing, and readout

The classical 3T MAPS pixel comprises a collection diode, reset transistor, source-follower input transistor, and row-select transistor. During integration, the diode collects charge and changes the sensing-node voltage. The source follower transfers the signal to a column readout circuit. Correlated double sampling (CDS) can remove reset-related $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$6 noise and fixed-pattern offsets by subtracting a post-reset reference from the integrated signal.

Self-bias pixels replace the reset transistor with a high-resistance forward-biased diode. The diode continuously compensates leakage current, eliminating an explicit reset cycle. The signal decays approximately as

$$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$7

where $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$8 is the signal-clearing time. Self-bias operation suppresses some dark-rate and reset effects, but increased leakage shortens $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$9, potentially clearing part of a physical signal before readout (Deveaux, 2019).

More advanced MAPS include a charge-sensitive amplifier (CSA), discriminator, threshold-adjustment DAC, local hit storage, and time-over-threshold (ToT) or time-of-arrival (ToA) logic. For a CSA with continuous feedback, the discriminator output remains active while the signal exceeds threshold. The resulting ToT is

$10~\Omega\cdot\mathrm{cm}$0

and can serve as a proxy for deposited charge after calibration.

Column-parallel and column-drain architectures replace full-frame analog scanning with sparse readout. In a column-drain system, hit pixels store local state and are selected by a priority token. Data are transferred toward end-of-column logic, where addresses, timestamps, and ToT information are serialized. The architecture may operate continuously, triggerlessly, or with trigger latency and local buffering. Gray-coded bunch-crossing counters are frequently used to reduce simultaneous switching activity, although TJ-Monopix2 demonstrated that distributed counter transitions can still induce substantial analog cross talk (Schall et al., 2024).

Fully monolithic sensors integrate functions that would ordinarily reside in a separate ASIC. MuPix7, for example, incorporated amplification, discrimination, address generation, time-stamp sampling, zero suppression, state-machine control, data encoding, serialization, and a $10~\Omega\cdot\mathrm{cm}$1 output link. Its $10~\Omega\cdot\mathrm{cm}$2-bit timestamps were generated at $10~\Omega\cdot\mathrm{cm}$3, and its PLL and serial link remained operational after the tested proton and neutron irradiations (Augustin et al., 2017).

The choice of readout architecture depends on the application. MuPix was developed for continuous, triggerless operation in Mu3e, whereas ATLASPix targets LHC operation with triggered readout, although some versions also support continuous streaming for testing. MuPix8 places amplification in the pixel but sends analog signals over lines up to approximately $10~\Omega\cdot\mathrm{cm}$4 to peripheral comparators, producing row-dependent cross talk and timing. ATLASPix places discrimination in the pixel, avoiding long analog paths at the cost of increased in-pixel area and capacitance (Schöning et al., 2020).

3. Collection electrodes, substrates, and process architectures

Large-electrode DMAPS

Large-electrode devices use a deep n-well as both the charge-collection electrode and the body region containing the CMOS electronics. A deep p-well shields the electronics and permits both NMOS and PMOS transistors inside the pixel. The large n-well creates a broad depleted region and comparatively uniform electric field, which favors rapid drift collection and radiation tolerance.

The disadvantage is high sensor capacitance. LF-Monopix, fabricated in a $10~\Omega\cdot\mathrm{cm}$5 LFoundry high-voltage CMOS process, has approximately $10~\Omega\cdot\mathrm{cm}$6 sensor capacitance, approximately $10~\Omega\cdot\mathrm{cm}$7 power consumption, and approximately $10~\Omega\cdot\mathrm{cm}$8 analog power density. Its $10~\Omega\cdot\mathrm{cm}$9 pixels use a high-resistivity p-type substrate, a large deep n-well, an AC-coupled CSA, and a 4-bit threshold DAC.

After neutron irradiation to $4\text{--}20~\mu\mathrm{m}$0 and $4\text{--}20~\mu\mathrm{m}$1 of background TID, LF-Monopix retained a detection efficiency of $4\text{--}20~\mu\mathrm{m}$2 in a $4\text{--}20~\mu\mathrm{m}$3 electron beam at $4\text{--}20~\mu\mathrm{m}$4, with noise occupancy below $4\text{--}20~\mu\mathrm{m}$5. Its ENC increased from $4\text{--}20~\mu\mathrm{m}$6 to $4\text{--}20~\mu\mathrm{m}$7, while the charge-to-voltage gain remained approximately $4\text{--}20~\mu\mathrm{m}$8. The post-irradiation breakdown voltage remained approximately $4\text{--}20~\mu\mathrm{m}$9 (Moustakas et al., 2018).

The preceding LF-CPIX and LF-Monopix1 development line demonstrated high-voltage operation, breakdown voltages near $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$0, $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$1-scale timing, and approximately $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$2 efficiency after neutron irradiation to $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$3. The LF-Monopix1 analog front end used a peaking time of approximately $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$4, $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$5 timestamping, an $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$6-bit leading-edge timestamp, an $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$7-bit trailing-edge timestamp, and $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$8 LVDS serialization (Barbero et al., 2019).

H35DEMO extended the large-electrode concept to a $W\propto\sqrt{\frac{\rho V_{\mathrm{bias}}}{ }},$9 AMS HV-CMOS process. It used a Deep N-Well in p-type substrates with resistivities of $\rho$0, $\rho$1, $\rho$2, and $\rho$3. In the $\rho$4 configuration, the device exceeded $\rho$5 efficiency after irradiation to $\rho$6 at bias above approximately $\rho$7. At $\rho$8, approximately $\rho$9 efficiency and noise occupancy below $V_{\mathrm{bias}}$0 per $V_{\mathrm{bias}}$1 bunch crossing were obtained. Above $V_{\mathrm{bias}}$2, efficiency fell below $V_{\mathrm{bias}}$3 because available bias and threshold margins were insufficient (Terzo et al., 2018).

Small-electrode DMAPS

Small-electrode architectures minimize sensor capacitance by separating the collection electrode from the in-pixel electronics. TJ-Monopix used a small n-well electrode in a modified TowerJazz $V_{\mathrm{bias}}$4 process. A planar n-layer extended depletion laterally through the $V_{\mathrm{bias}}$5 high-resistivity epitaxial layer. The sensor capacitance was approximately $V_{\mathrm{bias}}$6 or less.

Before irradiation, TJ-Monopix achieved approximately $V_{\mathrm{bias}}$7 ENC, a threshold near $V_{\mathrm{bias}}$8, threshold dispersion of $V_{\mathrm{bias}}$9, and noise occupancy near $80$0. After $80$1 and $80$2, the measured ENC was $80$3, threshold $80$4, and threshold dispersion $80$5. The chip remained functional, but a complete post-irradiation beam-efficiency measurement was not reported. Earlier modified-process test-chip measurements achieved charge-collection efficiency above $80$6 after $80$7 (Moustakas et al., 2018).

MALTA and related small-electrode devices showed the principal weakness of this architecture: field-free or weak-field regions near pixel borders and corners. MALTA used $80$8 pixels with diode capacitance below $80$9. After $10\text{--}15~\mu\mathrm{m}$0, its centre efficiency was approximately $10\text{--}15~\mu\mathrm{m}$1, while edge efficiency could fall to $10\text{--}15~\mu\mathrm{m}$2. Double-modified processes, involving interruption of the n-layer or addition of a deep p-region, were proposed to generate lateral fields in these regions (Deveaux, 2019).

TJ-Monopix2 expanded the approach to a $10\text{--}15~\mu\mathrm{m}$3 matrix with $10\text{--}15~\mu\mathrm{m}$4 pixels on a roughly $10\text{--}15~\mu\mathrm{m}$5 chip. Its sensor capacitance was approximately $10\text{--}15~\mu\mathrm{m}$6, analog power approximately $10\text{--}15~\mu\mathrm{m}$7 per pixel, and measured noise approximately $10\text{--}15~\mu\mathrm{m}$8. However, the distributed $10\text{--}15~\mu\mathrm{m}$9 BCID counter generated a periodic threshold modulation of up to $1000\text{--}1200~e^-$0, compared with approximately $1000\text{--}1200~e^-$1 ENC. The modulation had dominant Fourier components at $1000\text{--}1200~e^-$2 and $1000\text{--}1200~e^-$3, matching Gray-counter switching frequencies. The effect increased threshold dispersion from approximately $1000\text{--}1200~e^-$4 to as much as $1000\text{--}1200~e^-$5, demonstrating that mixed-signal coupling can dominate intrinsic analog noise in large matrices (Schall et al., 2024).

SOI and high-voltage CMOS

SOI-MAPS separate the electronics from the sensor substrate using a buried oxide (BOX). XTB01 was fabricated in a $1000\text{--}1200~e^-$6 thick-film HV-SOI process with a p-type $1000\text{--}1200~e^-$7 handle wafer, an n-type collecting diode, and a deep non-depleted isolation implant between the BOX and active circuitry. The isolation implant is intended to reduce back-gate modulation from radiation-induced charge trapped in the BOX.

XTB01 used $1000\text{--}1200~e^-$8, $1000\text{--}1200~e^-$9, and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$00 pixels, a standard 3T readout, and lateral high-voltage bias because the prototype lacked a backside implant. Approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$01 of depleted silicon was expected at $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$02. Before irradiation, particle signals of $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$03 and ENC near $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$04 were measured. After neutron exposure to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$05, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$06 pixels retained approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$07. At $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$08, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$09 pixels retained a similar signal, whereas $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$10 pixels showed no clear clustered signal, attributed to inter-pixel trapping and insufficient electric field (Hemperek et al., 2014).

4. Radiation effects and hardening strategies

Radiation affects MAPS through total ionizing dose (TID), displacement damage or NIEL, random telegraph signal (RTS), single-event effects, and thermal feedback.

TID produces electron–hole pairs in SiO$$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$11. Holes become trapped in oxide defects and at silicon–oxide interfaces, modifying surface potential, transistor threshold voltage, leakage paths, gain, discriminator thresholds, and bias currents. Thick shallow-trench isolation is often more vulnerable than the gate oxide itself. Narrow transistors are particularly sensitive. Thin gate oxides reduce oxide trapping through electron tunnelling.

Displacement damage displaces silicon atoms and creates recombination and trapping centres. The radiation-induced leakage current is commonly parameterized as

$$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$12

where $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$13 is the temperature-dependent damage constant, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$14 is equivalent fluence, and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$15 is depleted volume. Increased leakage raises shot noise and can cause thermal runaway. Trapping reduces carrier lifetime and charge-collection efficiency, especially in small-signal devices or regions with long collection paths.

Acceptor removal can temporarily reduce effective doping, enlarge depletion depth, and improve charge collection. At higher fluence, stable acceptor introduction and reverse annealing can increase effective doping again. Proton and neutron irradiation can therefore produce different depletion and leakage behavior even at comparable nominal fluence.

RTS arises when individual traps switch between occupied and unoccupied states. It is more pronounced in small transistors and at low drain currents. RTS can create spikes, hot pixels, dark-hit trains, and threshold instability. In EPCB01, all variants exhibited a significant RTS component associated with current fluctuations in very small transistors (Havránek et al., 2014).

Hardening strategies include high-resistivity epitaxial or bulk silicon, high-voltage depletion, deep p-wells and quadruple-well structures, modified n-layers for lateral depletion, enclosed-layout transistors, guard rings, pseudo-gates, leakage-routing structures, larger source-follower gates, cooling, faster readout, current-limited power supplies, and redundant control registers. Each introduces trade-offs. Larger transistors reduce RTS but increase capacitance; multiple collection diodes shorten paths but can increase noise; smaller pixels improve radiation tolerance but increase channel count and digital power (Deveaux, 2019).

Radiation qualification must distinguish TID and NIEL and account for irradiation bias, temperature, annealing, dose rate, particle species, and device history. Some studies used X-rays to isolate TID, reactor neutrons for displacement damage, and protons or pions for simultaneous ionizing and displacement damage. Cold neutrons can activate boron-related reactions not represented by standard NIEL scaling.

The most mature results demonstrate that fully depleted monolithic sensors can approach LHC requirements. LF-Monopix and related devices achieved approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$16 efficiency after $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$17, while ATLASPix1 maintained efficiencies above $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$18 after neutron fluences up to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$19 at suitable bias and noise conditions. MuPix7 remained operational after neutron fluences up to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$20 and proton fluences up to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$21, with timing better than $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$22, although efficiency and noise degraded at high fluence (Augustin et al., 2017).

5. Demonstrated detector technologies and applications

LHC and HL-LHC tracking

The LFoundry $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$23 DMAPS program targeted the ATLAS Inner Tracker. LF-CPIX and LF-Monopix used $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$24 pixels, large collection electrodes, high-resistivity substrates, high-voltage bias, and column-drain readout. LF-Monopix combined a $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$25 post-irradiation efficiency with noise occupancy below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$26 at $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$27. H35DEMO similarly demonstrated approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$28 efficiency after $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$29 at $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$30, but its breakdown and digital-crosstalk limitations motivated migration toward $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$31 processes (Barbero et al., 2019).

ATLASPix1 used local discrimination to avoid long analog routes. At $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$32, single-hit efficiencies exceeded $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$33 with practically negligible noise in unirradiated devices. After neutron irradiation, efficiencies of $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$34 at $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$35 were obtained in $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$36 devices at $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$37. Corrected timing was approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$38, with internal timing resolution approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$39 after subtracting timestamp sampling (Schöning et al., 2020).

ALICE and low-mass vertexing

ALPIDE established large-scale deployment of MAPS in high-energy physics. Fabricated in a TowerJazz $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$40 CMOS imaging process, it uses a high-resistivity p-type epitaxial layer, deep p-wells, in-pixel amplification, discrimination, buffering, and asynchronous priority-encoded zero-suppressed readout. Its $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$41 pixels provide approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$42 spatial resolution, detection efficiency above $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$43, fake-hit probability below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$44 hits/pixel/event, and front-end power below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$45. ALPIDE was operated after $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$46 TID and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$47 (Colella, 2024).

The ALICE ITS2 contains approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$48 ALPIDE sensors over approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$49, arranged in seven cylindrical layers. The innermost layers use $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$50-thick sensors and the outer layers $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$51-thick sensors. ALPIDE is also used in the Muon Forward Tracker and was selected for the highly granular electromagnetic component of the Forward Calorimeter.

ITS3 extends the concept to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$52 CMOS, wafer-scale stitching, thinning below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$53, and bending into half-cylindrical layers with radii of $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$54, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$55, and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$56. The intended sensors are approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$57 long, with target power below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$58, material below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$59 per layer, and air cooling. MLR1 test structures demonstrated approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$60 detection efficiency, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$61-class spatial resolution, and an APTS-OA timing resolution of $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$62. The modified-with-gap process generally provided the strongest charge-collection performance. The full-length stitched, thinned, bent ITS3 sensor remained a subsequent validation objective (Buckland, 2023).

Precision timing

A SiGe BiCMOS MAPS prototype demonstrated approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$63 timing without internal avalanche gain. Fabricated in a $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$64 SiGe process, it used fast SiGe HBT preamplifiers located close to hexagonal sensing pixels. Small pixels had approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$65 capacitance and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$66 ENC; large pixels had approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$67 and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$68 ENC. Time walk was below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$69 after ToT-based correction, and measured Gaussian-core timing resolutions reached $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$70 for small pixels and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$71 for large pixels. The quoted values describe the Gaussian core, with non-Gaussian tails of $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$72 and $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$73 for the small and large pixels, respectively (Iacobucci et al., 2019).

Future colliders and CEPC

TaichuPix1 investigated $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$74 pixels and fast in-pixel readout for a CEPC vertex detector. Its $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$75 matrix combined an ALPIDE-inspired analog front end with an FE-I3-like column-drain architecture. The FE-I3-like half operated at a $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$76 system clock, used in-pixel hit storage, and demonstrated triggered and triggerless readout. A serializer operated to approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$77, below the $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$78 design target. The estimated power was approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$79, substantially above the approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$80 quoted for ALPIDE. Triggerless operation suffered data loss when simultaneous hits exceeded the available arbitration and buffering capacity (Wu et al., 2021).

TANGERINE investigates $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$81 CMOS imaging technology for future lepton or Higgs factories and beam telescopes. Its goals include spatial resolution below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$82, temporal resolution below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$83, and total detector thickness below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$84. The first $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$85 pixel test chip demonstrated $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$86 analog rise times but revealed a layout flaw that restricted efficient detection to a few micrometres around the collection electrode. Future versions were planned with a $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$87 matrix, $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$88 pitch, and an 8-bit counter in every pixel (Chauhan et al., 2022).

Energy-loss measurement and gamma-ray detection

TIIMM extends MAPS beyond binary tracking by adding a 6-bit ToT measurement for ion-species identification. TIIMM-0 used $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$89 pixels and a $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$90 feedback capacitor; TIIMM-1 increased the feedback capacitance to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$91, expanding the simulated linear input-charge range from approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$92 to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$93. The simulated ENC increased from $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$94 to $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$95, while predicted pulse-width fluctuation decreased from as much as $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$96 to below $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$97. The reported laboratory results validated analog and digital functionality but did not yet establish absolute ToT calibration, energy resolution, or ion-identification power (Ren et al., 2022).

AstroPix adapts HV-MAPS to space-based keV–MeV gamma-ray telescopes. Its pixels combine charge collection, amplification, discrimination, ToT, and digital readout, supplying two-dimensional interaction positions without long silicon strips or per-pixel bump bonds. AstroPix-v1 used $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$98 pixels on approximately $$\Delta V\simeq\frac{Q_{\mathrm{sig}}}{C_{\mathrm{in}}},$$99-thick wafers. AstroPix-v2 used $10~\Omega\cdot\mathrm{cm}$00 pixels, restored functional digital readout, reduced analog power from $10~\Omega\cdot\mathrm{cm}$01 to $10~\Omega\cdot\mathrm{cm}$02, and achieved $10~\Omega\cdot\mathrm{cm}$03 FWHM at $10~\Omega\cdot\mathrm{cm}$04 in single-pixel analog measurements. The target is less than $10~\Omega\cdot\mathrm{cm}$05, approximately $10~\Omega\cdot\mathrm{cm}$06 pixels, $10~\Omega\cdot\mathrm{cm}$07 silicon, and a dynamic range of approximately $10~\Omega\cdot\mathrm{cm}$08 (Steinhebel et al., 2022).

6. Performance trade-offs and unresolved challenges

MAPS performance is governed by coupled sensor, circuit, readout, thermal, and mechanical constraints.

Capacitance versus radiation tolerance: large collection electrodes provide broad depletion, short collection paths, and high radiation tolerance, but increase capacitance, ENC, signal rise time, crosstalk, and analog power. Small electrodes provide capacitances near $10~\Omega\cdot\mathrm{cm}$09, very low ENC, low thresholds, and low power, but require lateral field engineering and are more sensitive to weak-field regions and radiation-induced trapping.

Depletion versus bias and breakdown: increasing substrate resistivity and reverse bias enlarges the depleted volume and improves drift collection. High voltage requires guard rings, insulation, breakdown control, leakage-current management, and cooling. After irradiation, leakage current can cause thermal runaway, particularly in highly integrated digital matrices.

Pixel pitch versus efficiency and resolution: small pixels improve spatial resolution and reduce charge-collection distance, but increase transistor count, routing complexity, power, data volume, and sensitivity to defects. Larger pixels generally provide greater charge-sharing margin but can increase capacitance and reduce granularity. The binary resolution is approximately

$10~\Omega\cdot\mathrm{cm}$10

where $10~\Omega\cdot\mathrm{cm}$11 is pixel pitch; charge sharing can improve on this limit when the analog response is sufficiently uniform.

Readout speed versus power: asynchronous priority encoding and sparse readout reduce data volume and support high rates, but distributed digital logic can inject noise into analog circuitry. The TJ-Monopix2 threshold modulation demonstrates that synchronous clock activity can overwhelm intrinsic ENC even when digital signals are Gray encoded. MuPix8 shows the converse problem: reducing in-pixel logic by moving discrimination to the periphery can create long analog interconnects and row-dependent cross talk.

Radiation hardness versus signal margin: depleted drift collection improves radiation tolerance, but high NIEL fluence still produces trapping and leakage. At high thresholds, charge-sharing regions and pixel corners are especially vulnerable because each pixel receives less charge. Cooling reduces leakage and noise but increases system complexity and may conflict with ultra-low material budgets.

Analog charge measurement versus binary detection: ToT provides charge or energy information without a full analog readout, but requires calibration, stable feedback, controlled pulse shapes, sufficient dynamic range, and low pixel-to-pixel variation. Increasing feedback capacitance extends dynamic range while increasing ENC. The relationship between ToT and deposited charge may become nonlinear through slew-rate dependence, saturation, threshold variation, and ballistic deficit.

Wafer scale versus yield and mechanical reliability: stitching enables sensors tens of centimetres long and reduces module boundaries, services, and support material. However, defects affect larger active areas, and wafer-scale sensors introduce handling, thinning, bending, power-distribution, yield, and assembly challenges. ITS3 targets approximately $10~\Omega\cdot\mathrm{cm}$12-long sensors thinner than $10~\Omega\cdot\mathrm{cm}$13, but full-scale stitched, bent, air-cooled detector layers require validation beyond small test structures.

The principal unresolved issues are complete radiation qualification under combined TID and NIEL exposure, operation at realistic temperature and bias conditions, suppression of RTS and mixed-signal cross talk, uniform charge collection across large matrices, scalable buffering and data transmission, production yield, power and cooling, and detector-level integration. The evolution from conventional diffusion-based MAPS to high-resistivity depleted sensors has established drift collection, integrated fast readout, and LHC-scale radiation tolerance. The remaining development problem is not a single device parameter but the simultaneous optimization of electric-field geometry, collection-electrode capacitance, transistor layout, digital architecture, thermal management, mechanical structure, and system-level data flow.