Parallel One-Bit ADCs (PO-ADCs)

• Parallel One-Bit ADCs (PO-ADCs) are receiver architectures that digitize high-dimensional signals using multiple one-bit converters, offering efficient alternatives to high-resolution ADCs in applications like massive MIMO and radar.
• They employ techniques such as Bussgang linearization, adaptive thresholding, and advanced signal processing to mitigate nonlinearity and quantization distortion while maintaining performance.
• PO-ADC systems enable significant power savings and reduced hardware complexity by distributing quantization tasks across parallel channels, balancing energy efficiency with achievable rates.

Parallel One-Bit ADCs (PO-ADCs) are receiver architectures that utilize multiple one-bit analog-to-digital converters operating in parallel to digitize high-dimensional or high-rate analog signals, most prominently in massive MIMO, wideband communications, radar, and spectrum sensing applications. The primary driver for PO-ADC architectures is the exponential growth in power and hardware complexity associated with increasing ADC resolution. By leveraging the physical and algorithmic properties of having numerous one-bit quantization operations performed in parallel and often coordinated with analog and digital pre- and post-processing, these architectures aim to achieve performance approaching that of high-resolution ADC systems at a fraction of the energy and circuit cost.

1. Power Efficiency and Architectural Rationale

The core advantage of PO-ADCs is rooted in the drastically reduced power consumption of a one-bit comparator relative to conventional high-resolution ADCs. In a parallel architecture, each sample is processed with a separate one-bit comparator, and system-wide resolution and dynamic range targets are achieved by distributing ADC “tasks” across multiple one-bit branches with appropriate analog front-end design. Whereas the power for a conventional n-bit flash ADC scales as $P_{\text{conv}}\sim f_s 2^{2n}$, the per-channel power in a PO-ADC scales linearly with sampling rate, $P_{\text{1bit}}\sim f_s$ (Mulleti et al., 2023). Interleaving and architectural choices (e.g., time, space, or frequency division) allow aggregate sampling rates and dynamic range to be matched to the application. Techniques such as sub-Nyquist sampling, modulo analog preprocessing, or level-crossing sampling further exploit signal structure or temporal sparsity to minimize per-channel ADC power (Mulleti et al., 2023).

2. Signal Processing Principles and Quantization Effects

PO-ADC systems are characterized by the nonlinearity imposed by one-bit quantization. In the generic model, the quantized output $q_i[m]$ from each branch is

$q_i[m] = \mathcal{Q}(u_i[m] + n_i[m])$

where $\mathcal{Q}(\cdot)$ maps the input (usually complex) to the sign of its real and imaginary components. Despite severe amplitude information loss, in high-dimensional settings such as massive MIMO, the aggregate effect of quantization can often be analytically “linearized” using the Bussgang theorem or related tools, showing that the quantized outputs behave like scaled linear functions of their analog precursors plus uncorrelated distortion (Nguyen et al., 2019, Nguyen et al., 2020, Kim et al., 2019). This enables the design of linear, low-complexity receivers (e.g., Bussgang-based MRC, ZF, MMSE) that can mitigate, to an extent, the quantizer nonlinearity.

In wideband or frequency-selective channels, per-symbol variations in received power (the “amplitude distortion” term) are shown to vanish as the number of channel taps increases, leaving a circularly symmetric (essentially Gaussian) quantization distortion. In this regime, the difference in achievable rate between OFDM and single-carrier transmission vanishes, and linear processing suffices (Mollén et al., 2016).

3. Channel Estimation, Detection, and Decoding Algorithms

PO-ADC systems require channel estimation algorithms robust to coarse quantization. Practical low-complexity LMMSE estimators, iterative joint pilot-and-data (JPD) expectation-maximization techniques, and specialized compressive sensing algorithms are all employed to recover the channel state (Mollén et al., 2016, Kim et al., 2019, Liu et al., 15 Aug 2025).

Channel estimation frameworks frequently utilize pilot orthogonality, phase randomization, and frequency-domain representations. For mmWave or angularly structured channels, hybrid amplitude retrieval algorithms or direction-of-arrival approaches (e.g., MIPS: maximum inner product search) exploit preserved angular/coherence structure even after one-bit quantization, though amplitude recovery is fundamentally hampered at high SNR (Kim et al., 2018, Qian et al., 2019). In temporally and spatially correlated channels, recursive Kalman filtering with Bussgang decomposition improves channel tracking, while approximations such as truncated polynomial expansion lower computational complexity (Kim et al., 2019).

Detection and decoding leverage weighted Hamming/sphere decoding, sequential or greedy list-based search methods, and deep unfolding of iterative optimization as model-driven neural networks. In uplink scenarios, parallel processing is exploited by dividing quantized data into sub-vectors, each processed independently to reduce sphere decoding complexity while approaching the maximum-likelihood error rate (Jeon et al., 2017). Successive-cancellation, soft-output detectors further exploit previous decodes to refine LLR computations for use in powerful modern error-correction decoders (Cho et al., 2017, Ivanov et al., 2022).

4. Capacity, Achievable Rate, and System-Level Tradeoffs

Closed-form expressions for spectral efficiency and achievable rates with PO-ADCs reveal explicit trade-offs between array size, quantization loss, pilot overhead, and SNR. For example, the achievable rate for $K$ users in a massive MIMO uplink with one-bit ADCs is given (assuming many channel taps and linear channel estimation) by:

$$R_k = \log_2 \left(1 + \frac{c_k \beta_k P_k G_k}{\sum_{k'} \beta_{k'} P_{k'} (1 - c_{k'} (1 - I_{kk'})) + N_0 + Q'} \right)$$

where $Q'$ (the quantization distortion variance, tending to $\bar{P}_{\text{rx}} (\pi/2 - 1)$ in the wideband limit) does not decrease with antenna number, but the array gain $G_k$ does scale with array size (Mollén et al., 2016). This leads to the principal regime where quantization loss can be offset simply by scaling the number of antennas (requiring roughly $2.5$--$3\times$ as many one-bit antennas as high-resolution ones to achieve a given rate at low/moderate SNR). At high SNR, however, residual non-Gaussian quantization noise imposes a fundamental rate ceiling (Mollén et al., 2016, Deng et al., 2021).

In point-to-point and broadcast multi-terminal MIMO, architectural choices such as adaptive-threshold PO-ADCs—where the threshold at each quantizer is dynamically adjusted across channel uses—can achieve the full aggregate rate corresponding to the number of parallel ADCs at high SNR, eliminating the otherwise typical “rate saturation” observed in one-shot, fixed-threshold designs (Khalili et al., 2019, Khalili et al., 2021). Achievable rate regions for such receivers approach the theoretical maximum as SNR increases.

Analog preprocessing with nonlinear operations, implemented with practical circuit elements, can also increase achievable information rates by reshaping received signal statistics before quantization, yielding finer quantization regions and enhanced capacity (Shirani et al., 2022).

5. Coding, Error Correction, and Detection Performance

PO-ADC receivers operating over AWGN or fading channels transform the effective channel into a binary symmetric channel (BSC), rendering traditional soft-decision decoding suboptimal unless soft information is synthesized from the statistics of the one-bit outputs. Channel-dependent polar and LDPC codes (with density-evolution construction or ACE extension), list decoding, and iterative sum-product algorithms are shown to yield close-to-capacity performance when log-likelihood ratios are accurately approximated using system knowledge (e.g., $p = Q(\sqrt{\text{SNR}})$ for the BSC crossover parameter) (Ivanov et al., 2022). At very high rates and SNRs, BCH and product codes (with hard-decision decoders) perform best due to their tailored minimum distance properties.

The parallel structure of PO-ADCs can be directly exploited by distributing coded symbols and channel measurement diversity across independent one-bit outputs to yield improved FER, leveraging redundancy and diversity effects in code design (Ivanov et al., 2022).

6. Sensing, Spectrum, and Radar with Parallel One-Bit ADCs

PO-ADCs find critical application in power- and hardware-constrained signal acquisition tasks far beyond communications. In wideband spectrum sensing, non-cooperative architectures combining sub-Nyquist multicoset sampling with parallel one-bit ADCs allow low-power acquisition and spectrum estimation without prior sparsity or multi-user cooperation (Yang et al., 7 Nov 2024). Bussgang-based linearizations are employed to analyze the effect of quantization and to design blind detection and support estimation from eigenvalue decompositions of quantized covariance matrices. Despite the severe loss of amplitude, PO-ADC spectrum sensing can recover the spectral support accurately, provided the sample support is increased to compensate for quantization noise.

In radar, PO-ADCs are used to perform high-speed sampling with time-varying thresholds or carefully designed analog preprocessing to maximize the information extractable from each one-bit channel. Target parameter estimation (e.g., range, Doppler) is formulated as weighted least-squares problems under one-bit sign constraints, and parallelism in sampling is used to improve both estimation accuracy and speed (Ameri et al., 2019). Performance loss due to quantization can be quantified, such as an inherent QSINR loss of approximately $2/\pi \approx 1.96$ dB at low SNR, which can be offset in practice by using more samples or enhanced analog design (Deng et al., 2021, Wu et al., 2023).

7. Future Directions and Open Challenges

Research points to several frontiers for PO-ADCs. Practical nonlinear analog preprocessing (to increase quantization region count), adaptive-threshold architectures (to maximize per-ADC effective resolution), and integration with compressive and task-based sampling frameworks (to minimize power and hardware for a given estimation/detection task) are promising avenues for hardware-efficient design (Khalili et al., 2019, Shirani et al., 2022, Mulleti et al., 2023). Open challenges include optimizing channel estimation under extreme quantization, handling label uncertainty and non-Gaussian distortion in the likelihood models (e.g., with reinforcement learning frameworks (Jeon et al., 2019)), protocol design for distributed sensing and networked PO-ADC systems, and extending analog front-end innovations to fully exploit the digital algorithmic potential of parallel one-bit quantization.

PO-ADC architectures are thus at the intersection of hardware efficiency and modern high-dimensional signal processing, offering a principled and rapidly evolving toolkit for large-scale, energy-limited receiver design in next-generation wireless, radar, and sensing systems.