Native Spiking Microarchitecture

• Native spiking microarchitecture is an integrated hardware-software design that tightly couples spiking neuron models, event-driven computation, and local memory for optimized SNN execution.
• It employs asynchronous, spike-driven scheduling alongside custom ISA extensions and SIMD pipelines to achieve low-latency and energy-efficient performance.
• Scalable implementations leverage modular tiling and optimized dataflow to support large-scale networks with hundreds of thousands of neurons and millions of synapses.

A native spiking microarchitecture refers to an integrated hardware-software organization in which spiking neuron models, event-driven computation, spike communication, and memory structures are realized at the microarchitectural or circuit level, affording optimized, low-latency, and energy-efficient execution of spiking neural networks (SNNs). Unlike systems that emulate spiking dynamics atop conventional digital datapaths or neural instruction sets designed for analog neurons, a native spiking microarchitecture tightly couples neuron/synapse models, spike event routing, local state storage, and (in many designs) programmability, directly into processor pipelines or mixed-signal circuit fabrics.

1. Architectural Fundamentals and Design Principles

Native spiking microarchitectures instantiate event-based, sparse computation as a first-class design feature, moving beyond the abstraction of generic multiply-accumulate pipelines or densely clocked synchronous update engines. Core design principles include:

• Tight Locality of State and Processing: Compute engines (often termed Processing Elements, PEs) embed local memories for neuron state variables, synaptic weights, and plasticity tables, minimizing large-scale data shuttling and alleviating the classic von Neumann bottleneck (Agrawal et al., 2017).
• Event-Driven or Mixed-Driven Execution: System-level scheduler architectures operate in a strictly spike-driven (asynchronous) manner (Richter et al., 2023, Anand et al., 2023), a highly clocked synchronous mode with cycle skipping (for sparse activity) (Carpegna et al., 2022), a temporally batched mode (Xu et al., 18 May 2025), or via decoupled logic that processes spike time independently of processing clock (Windhager et al., 2023).
• Programmability and ISA Extensions: Custom instructions or pipelines are introduced for neuron and synapse updates, e.g., dedicated neuromorphic instructions in RISC-V extensions (IzhiRISC-V: nmpn, nmdec) or 30-bit vector ops for parallel event execution (Szczerek et al., 18 Aug 2025, Aizaz et al., 1 Nov 2025, Aizaz et al., 13 Jun 2025).
• Scalability via Modular Tiling and Hierarchy: Native architectures often tile neuron/synapse fabrics or PEs in grids or hierarchies (2D mesh, multi-core, crossbar, systolic array) (Agrawal et al., 2017, Aizaz et al., 1 Nov 2025, Richter et al., 2023, Xu et al., 18 May 2025).

2. Circuit and Compute Models

The neuron models underpinning native microarchitectures vary in biological fidelity and arithmetic complexity:

• Leaky Integrate-and-Fire (LIF): Realized in both pure-digital fixed-point/shift circuitry (Carpegna et al., 2022, Windhager et al., 2023) and ultra-compact subthreshold analog CMOS (Besrour et al., 14 Aug 2024). The dynamics are governed by $$C_{\text{mem}}\frac{dV_{\text{mem}}}{dt} = -\frac{V_{\text{mem}} - V_{\text{reset}}}{R_m} + I_{\text{syn}}$$ and are mapped onto either analog capacitors and comparators (analog) or add-shift pipelines (digital).
• Izhikevich: Supports complex spiking/bursting with quadratic terms and recovery variables $$v_{n+1} = v_{n} + h\bigl(0.04 v_n^2 + 5v_n + 140 - u_n + I_{\text{syn},n}\bigr),\quad u_{n+1} = u_n + h a(b v_n - u_n)$$ computed via custom ISA in a single cycle (IzhiRISC-V nmpn instruction) (Szczerek et al., 18 Aug 2025).
• Quadratic, Adaptive and Hodgkin-Huxley: Integer-QIF neurons offer piecewise-linear dynamical branches, integrated in pipeline datapaths (Yeh et al., 2022), and more complex conductance-based models (e.g., HH with multi-LUT lookup per time step) are implemented in memory-rich PEs using ROM-embedded RAM primitives (Agrawal et al., 2017).
• Analog Neurons with Subthreshold Dynamics: Designs like DYNAP-SE2 and the 28 nm LIF neuron in TSMC employ a differential-pair integrator for membrane leak and summation, with programmable current sources for bias and refractory behavior (Besrour et al., 14 Aug 2024, Richter et al., 2023).

Synaptic computation is commonly based on weighted summation of binary or quantized spike inputs, with storage in local SRAM, ROM-embedded RAM, or crossbar arrays, supporting parallel R/W access per cycle (Agrawal et al., 2017).

3. Event-Flow, Communication Infrastructure, and Dataflow

Event delivery and routing mechanisms are diverse and tightly bound to architectural choices:

• Address-Event Representation (AER): Widely used for both on-chip and inter-chip spike routing. Each spike is encoded with a neuron (or PE) address and timestamp or delta, then transmitted asynchronously on a priority or handshake network (Richter et al., 2023, Besrour et al., 14 Aug 2024).
• Self-Timed and Asynchronous Schedulers: Spike “buses” and event arbiters (e.g., C3S Gamma-cycle controller, DYNAP-SE2 local router trees, AEQ spike queues) orchestrate the system in an event-driven regime, where the hardware operates strictly as real data flow permits (Anand et al., 2023, Richter et al., 2023, Sommer et al., 2022).
• Systolic Arrays and SIMD Event Pipelines: Designs such as SpikeX place neuron/synapse compute units in a spatially organized, data-driven mesh with temporal batching, recycling multi-bit weight fetches alongside batched binary spike streams for high energy reuse (Xu et al., 18 May 2025).
• Dataflow Optimization: Scheduling strategies maximize weight reuse, minimize spike/weight data movement, and adaptively exploit observed sparsity (e.g., activation-induced weight tailoring, batched NTWU dispatch) (Xu et al., 18 May 2025, Sommer et al., 2022).

4. Memory Organization, In-Memory Computation, and Scalability

Memory plays a central role:

• Local and Distributed In-PE Memory: To minimize data transport, weights, neuron/synapse states, and non-linear function LUTs are stored in the local memory of each PE/cluster (e.g., SPARE’s ROM-embedded RAM, FeNN's URAM or lane-BRAM) (Agrawal et al., 2017, Aizaz et al., 1 Nov 2025, Aizaz et al., 13 Jun 2025).
• ROM-Embedded Primitives: SPARE’s R-SRAM and R-MRAM integrate dense LUT storage alongside RAM bits in the same footprint, enabling arbitrary polynomial or exponential computation without extra area/power (Agrawal et al., 2017).
• Hierarchical and Crossbar Approaches: POPPINS uses SRAM banks per NPU, virtualized crossbar with sparse access for both recurrent and external input, supporting flexible and reconfigurable population-based mapping (Yeh et al., 2022).
• Tile-Based Mixed-Signal SoCs: Large mixed-signal systems tile analog neuron cores with embedded SRAM and interconnect via AER buses, attaining high neuron density at sub-femtojoule energies (Besrour et al., 14 Aug 2024, Richter et al., 2023).

Scalability is a function of memory bandwidth (often the ultimate bottleneck), local storage density, and event-communication architecture. Implementations have reached hundreds of thousands of neurons and >$10^8$ synapses per chip in theoretical scaling, with multi-chip AER fabrics (DYNAP-SE2: up to $65,536$ neurons in $8\times 8$ tiling) (Richter et al., 2023, Besrour et al., 14 Aug 2024).

5. Custom Instruction Sets and Programmability

Programmability in native spiking microarchitectures is achieved through custom ISA extensions and high-level DSL compilation:

• RISC-V Neuromorphic Extensions: IzhiRISC-V introduces dedicated nmpn and nmdec instructions for single-cycle Izhikevich and synaptic decay update, mapped to custom datapaths (NPU/DCU) in an augmented ALU pipeline. All operations use fixed-point arithmetics and Q-format encoding, enabling high-performance, low-energy execution indistinguishable from RISC-V scalar instructions in the code flow (Szczerek et al., 18 Aug 2025).
• SIMD Vector Processing: FeNN-DMA and FeNN exploit wide vector units (e.g., 32x16b SIMD, 512b registers), with 30-bit custom vector instructions for value, mask, and pseudorandom generation per lane (Aizaz et al., 1 Nov 2025, Aizaz et al., 13 Jun 2025).
• C-like Neuron Model DSLs and Event Kernel Compilation: Frameworks like PyFeNN generate hardware-executable code for arbitrary neuron/synapse models, including dense/compressed/delayed kernels and plasticity, decoupling SNN description from hardware re-synthesis (Aizaz et al., 1 Nov 2025).

6. Performance, Energy Efficiency, and Technology Mapping

Native microarchitectures achieve energy/throughput metrics unattainable in generic AI accelerators:

• Resource Utilization and Throughput: FPGA-based implementations (e.g., Spiker, FeNN-DMA, STI-SNN) reach 0.14–0.19 GOPS/W/PE and >98% accuracy on benchmarks, with sub-millisecond inference and per-spike energies from 1.61 fJ (analog) to 8–69 pJ (digital), large design space dictated by technology node and neuron model (Besrour et al., 14 Aug 2024, Wang et al., 10 Jun 2025, Aizaz et al., 13 Jun 2025, Aizaz et al., 1 Nov 2025, Yeh et al., 2022, Carpegna et al., 2022).
• Comparison to GPUs/CPUs/Fixed Pipelines: Native SNN accelerators consistently surpass standard ANN accelerators (GPU, TPU, CPU) in area/energy per synaptic op, e.g., FeNN outperforms Jetson Orin GPU (8 nJ/SOP vs 18 nJ/SOP) and Loihi (Aizaz et al., 13 Jun 2025).
• Physical Layer Innovations: Iontronic and MOF-channel designs (Tang, 8 Dec 2025) bridge stochastic physical substrates and deterministic, bit-exact spike logic. The spatial pipeline approach achieves $O(\log N)$ latency for linear layers and demonstrated 17× throughput advantage over temporal SNN summation, while retaining immunity to strong leakage and stochasticity (Tang, 8 Dec 2025).

7. Trade-Offs, Extensions, and Prospects

Key trade-offs and future directions include:

• Fixed-Point vs. Analog Precision: Lower bit-depths (4–6 bits for weights) suffice for >97% task accuracy; analog implementations provide minimal energy/spike but require offline or surrogate-gradient learning, and may suffer from process variation (Besrour et al., 14 Aug 2024, Windhager et al., 2023).
• Parallelism and Event Scheduling: Aggressive intra- and inter-layer parallelism (STI-SNN, FeNN-DMA, SpikeX) enables linear or superlinear throughput scaling, but demands careful RAM partitioning, NoC integration, and conflict-free event routing (Xu et al., 18 May 2025, Wang et al., 10 Jun 2025, Aizaz et al., 1 Nov 2025).
• Programmability vs. Specialization: Custom ISAs and vector abstractions (FeNN, IzhiRISC-V) tradeoff instruction overhead vs. adaptability to model innovation and dynamic neural computation (Szczerek et al., 18 Aug 2025, Aizaz et al., 13 Jun 2025).
• Full-Stack Network/Architecture Co-Design: Methods such as SpikeX-HAS and hardware-aware SNN training tune both network structure and accelerator configuration to minimize energy-delay product for given sparsity, enforcing tight coupling between software stack and native hardware (Xu et al., 18 May 2025).

Native spiking microarchitecture thus represents the technological convergence of event-driven computation, local memory integration, hardware-neuron co-design, and microarchitectural/ISA innovation for efficient, scalable realization of SNNs, from sub-femtojoule analog to fully digital and spatially pipelined combinational logic (Agrawal et al., 2017, Besrour et al., 14 Aug 2024, Szczerek et al., 18 Aug 2025, Aizaz et al., 1 Nov 2025, Richter et al., 2023, Xu et al., 18 May 2025, Aizaz et al., 13 Jun 2025, Tang, 8 Dec 2025).