Manarat: Multi-Board Quantum Control

• Manarat is a scalable multi-board control platform for superconducting quantum processors that achieves deterministic sub-100 ps timing alignment across AMD ZCU216 RFSoC boards.
• It enhances the QICK framework by integrating precise clock distribution, custom analog front-ends, and a novel SYNC instruction to enable coordinated hardware and firmware synchronization.
• Experimental validation on a 10-qubit transmon processor demonstrated uniform phase alignment, CZ gate fidelity of ~98.6%, and minimal crosstalk across boards.

Manarat is a scalable multi-board control platform for superconducting quantum processors built on the Quantum Instrumentation Control Kit (QICK) and AMD ZCU216 RFSoC boards. It introduces coordinated hardware, firmware, and software enhancements for deterministic multi-board operation, with sub-100 ps timing alignment across boards and validation on a 10-qubit flux-tunable transmon processor controlled by two RFSoC boards (Silva et al., 14 Jul 2025). In the source paper, Manarat addresses a specific limitation of QICK: although QICK offers a flexible open-source framework for pulse-level qubit control, it lacks native support for multi-board synchronization, which limits applicability to mid- and large-scale quantum devices.

1. System definition and architectural scope

Manarat extends Fermilab’s open-source QICK platform to support two, and in principle up to six, AMD ZCU216 RFSoC boards running in lock-step (Silva et al., 14 Jul 2025). Each ZCU216 carries 16×14-bit, 9.85 GS/s DAC channels, 16×14-bit, 2.5 GS/s ADC channels, and embedded ARM cores running PetaLinux/PYNQ. In the demonstrated configuration, control of a 10-qubit flux-tunable transmon processor is partitioned across two boards; each handles 5 drive lines, 5 flux lines, and one multiplexed readout line with up to 8 tones.

Within this architecture, the scaling problem is not merely channel count. The paper frames the central issue as coherent multi-qubit operations spanning beyond the capacity of a single control module. Manarat therefore targets synchronized control, deterministic program execution across boards, and integrated support for both fast RF pulse generation and software-programmable DC biasing. A plausible implication is that the platform is designed for regimes in which qubit control, flux tuning, and readout must all remain phase- and time-consistent across physically distinct control modules.

A plausible misconception is that QICK by itself already provides the required multi-board semantics. The paper states the opposite: QICK lacks native support for multi-board synchronization, and Manarat is introduced specifically to overcome that limitation (Silva et al., 14 Jul 2025).

2. Hardware organization and clock-distribution network

The hardware layer combines RFSoC boards, a shared timing reference, synchronization signaling, and a custom analog front-end. A single Analog Devices HMC7044 evaluation board generates a 7.68 MHz reference clock and up to six outputs. Phase-matched low-loss coaxial cables distribute the 7.68 MHz reference to each board’s CLK104 daughter card. Each CLK104 hosts a TI LMK04828 clock conditioner, locked in nested zero-delay dual-loop mode to the 7.68 MHz reference, producing DCLKout6 = 245.76 MHz for the DAC reference, DCLKout12 = 245.76 MHz for the ADC reference, DCLKout8 = 122.88 MHz for FPGA logic domains common across boards, and SCLKout9 = 7.68 MHz SYSREF for RFSoC Multi-Tile Synchronization (Silva et al., 14 Jul 2025).

The synchronization network includes a custom “Synchronization Signaling Bus” wired-AND circuit interconnecting one GPIO per board. When all tProcessors assert “ready,” the shared line rises and releases all tProcessors simultaneously. A Raspberry Pi monitors lock status of each HMC7044 PLL via SPI and SSH to the RFSoC; on loss-of-lock it reconfigures the HMC7044.

These elements establish the physical basis for cross-board determinism. The paper’s hardware claims are specifically about common reference generation, phase-matched distribution, and simultaneous release of program execution. This suggests that Manarat treats synchronization as a system property emerging from clock-tree design, converter alignment, and instruction-level release control rather than from software coordination alone.

3. Firmware mechanisms for deterministic synchronization

The firmware stack implements the clock tree, RFSoC Multi-Tile Synchronization, and modifications to the tProcessor instruction flow. The clock-tree implementation is described as HMC7044 → LMK04828 → MMCM → four internal clocks: pl_refclk = 122.88 MHz for the tProcessor and Sync IP, axi_aclk = 122.88 MHz for the AXI bus, axis_aclk = 368.64 MHz for the AXI-stream to DACs, and time_clock = 368.64 MHz for the tProcessor dispatcher (Silva et al., 14 Jul 2025).

RFSoC Multi-Tile Synchronization distributes SYSREF to all DAC and ADC tiles and engages the RFDC’s built-in synchronization state machine via the PYNQ xrfdc API and the Xilinx RFSoC-MTS package. The stated purpose is sub-cycle-level alignment of all converter samples across tiles and boards.

The key execution-control enhancement is the introduction of a new “SYNC” instruction in the tProcessor instruction set. On execution, the tProcessor drives GPIO to high-impedance to signal “ready,” stalls with fetch_en = 0 until external flag_i == 1 from Sync IP, and upon release resumes fetch_en = 1 on the same clock edge across all boards. The paper states that this eliminates the ±2-cycle uncertainty of the original tProcessor flush/fetch mechanism and guarantees three conditions: core clocks are phase-coherent through HMC7044 and LMK04828, external flags arrive simultaneously, and all tProcessors sample the flag in the same cycle (Silva et al., 14 Jul 2025).

The signal-generator configuration complements this synchronization model. The implementation uses 6 full-speed generators at 5.89824 GS/s for flux pulses, 6 interpolated generators at 5.89824 GS/s for drive pulses, 1 multiplexed signal generator with at most 8 tones at 5.89824 GS/s for readout, and 1 multiplexed read-in block with at most 8 channels at 2.4576 GS/s. The design also removes unused IP, including DDR4 and dynamic readouts, and integrates SPI drivers for the custom DC-DAC analog front-end.

4. Analog front-end for flux, drive, and readout control

A distinguishing component of Manarat is the custom analog front-end for flux control, which combines high-speed RF signals with software-programmable DC biasing voltages (Silva et al., 14 Jul 2025). The DC bias DAC is the TI DAC80508, with 8 channels, 16-bit resolution, and a ±2.5 V range. It is SPI-programmed by ARM/PYNQ at up to 150 kS/s, with noise spectral density of approximately $1 \,\text{nV}/\sqrt{\text{Hz}}$ and drift below $10 \,\mu\text{V}/\text{hr}$ after warm-up.

The RF path uses a Mini-Circuits TCBT-2R5G+ bias-tee. The DAC RF output, with maximum 6 GHz, is combined through the bias-tee with the DC DAC. The RF bandwidth is DC–2.5 GHz with insertion loss below 1 dB. The resulting output is a combined DC plus fast AC flux pulse path with sub-1 ns edge risetimes (Silva et al., 14 Jul 2025).

The paper gives idealized transfer functions for the bias-tee:

$$H_{\text{bias-tee}}(s) = \frac{R_{\text{load}}}{R_{\text{load}} + 1/(sC)}$$

with $C \approx 100\,\text{nF}$, setting $f_c \sim 10\,\text{Hz}$ for the DC path and a high-pass pole of approximately 1 MHz for the AC path.

For RF drive and readout, the XM655 analog front-end provides four 4–5 GHz baluns for drive tones and one 5–6 GHz balun for high-frequency qubits and readout. The reported outcome is adequate SNR despite slight off-band operation. In context, this front-end architecture allows Manarat to couple static flux biasing, fast flux modulation, microwave drive generation, and multiplexed readout into a single synchronized control stack.

5. Software stack and Qibo integration

The software layer comprises embedded Linux support, Python drivers, multi-board orchestration logic, and integration with Qibo. The embedded environment uses a PetaLinux BSP with a custom device tree covering SPI to the DC-DAC board, I²C to the LMK04828, and GPIO for the Sync bus (Silva et al., 14 Jul 2025). Python drivers are provided for the LMK04828 through xrfclk, the RFDC through xrfdc with MTS, the Sync IP, and the DC-DAC.

At the application level, the hardware driver implements the high-level Qibo Device API. The reported capabilities include multiplexed readout, waveform uploads, parameter sweeps, and sub-ns timing adjustments in 0.17 ns steps via padding. Calibrations and algorithms use QiboLab and QiboCal routines.

Multi-board orchestration is centralized. A master program compiles per-board tProcessor code and waveforms, ensures simultaneous “go” via the Sync instruction, aggregates results from all boards, and exposes them as a single logical device in Qibo (Silva et al., 14 Jul 2025). The paper also lists performance optimizations: ARM-side offload of compilation and parameter updates, pipelined upload and execution, multithreaded compile, and binned acquisitions with parallel sweeps for accelerated calibration.

This software organization indicates that Manarat is not only a synchronization mechanism but also an execution model in which multiple RFSoC boards are abstracted as one composite instrument. A plausible implication is that experiment control software can remain device-centric while the platform handles board-level partitioning internally.

6. Timing analysis, validation, and demonstrated performance

The paper provides a clock-jitter and timing-skew model:

$$\sigma_{\text{jitter}}^2 = \sigma_{\text{HMC7044}}^2 + \sigma_{\text{LMK04828}}^2 + \sigma_{\text{cable}}^2$$

with typical values $\sigma_{\text{HMC7044}} \lesssim 80\,\text{fs}$, $\sigma_{\text{LMK04828}} \lesssim 50\,\text{fs}$, and $\sigma_{\text{cable}} \lesssim 5\,\text{ps}$ for matching of at most 1 mm. Total timing uncertainty is given as

$$\Delta t_{\text{total}} = \sqrt{\sigma_{\text{jitter}}^2 + \sigma_{\text{skew}}^2} \le 100\,\text{ps}$$

with $10 \,\mu\text{V}/\text{hr}$0 from board-to-board cable length mismatch. The paper further states that, even conservatively,

$10 \,\mu\text{V}/\text{hr}$1

Experimental validation uses two ZCU216 boards, the custom flux analog front-end, the XM655 RF analog front-end, the HMC7044, CLK104, and the Sync bus to control 10 flux-tunable transmon qubits in a ladder with alternating 4.2/4.8 GHz qubits and 2 readout feedlines at approximately 7.5 GHz (Silva et al., 14 Jul 2025). Timing alignment measurements include an oscilloscope overlay of 10 000 square pulses at 100 ps/div with timing skew below 100 ps, Gaussian 4.5 GHz pulses with phase alignment within 200 fs, and a full control sequence of flux, drive, and readout with all edges within ±50 ps. The measured alignment error over 1 000 trials is reported as mean $10 \,\mu\text{V}/\text{hr}$2, $10 \,\mu\text{V}/\text{hr}$3.

The experimental program also includes simultaneous resonator-flux spectroscopy for all 10 qubit resonators swept versus DC bias in one shot, with uniform spectroscopic dip depth and SNR above 20 dB on all channels. For cross-board entangling control, the paper reports CZ chevrons for qubit pairs q2–q7 and q1–q6, where each pair spans different boards; the flux-pulse amplitude versus duration chevrons are clearly resolved, and the extracted oscillation frequency matches theory within 2 MHz (Silva et al., 14 Jul 2025). From chevron oscillation contrast and single-shot readout histograms, the paper infers a two-qubit conditional-phase fidelity $10 \,\mu\text{V}/\text{hr}$4. Coherence and crosstalk measurements report average $10 \,\mu\text{V}/\text{hr}$5, $10 \,\mu\text{V}/\text{hr}$6 for all 10 qubits, and crosstalk below 0.05 population leakage between simultaneously driven qubits on different boards.

Taken together, these results substantiate the paper’s central claim: by combining a low-jitter clock distribution using HMC7044 and LMK04828, custom Sync IP and tProcessor enhancements, and a dual RF plus DC analog front-end, deterministic sub-100 ps synchronization across multiple AMD ZCU216 RFSoC boards is achievable (Silva et al., 14 Jul 2025). This suggests that Manarat occupies an intermediate scaling point between single-board laboratory control and larger multi-module superconducting quantum computing systems, with the principal contribution lying in the explicit unification of clocking, instruction-level synchronization, analog biasing, and software orchestration.