LightMat-HP: Photonic-Electronic GEMM Accelerator

• LightMat-HP is a hybrid photonic–electronic accelerator system designed for high-precision GEMM using configurable block floating-point arithmetic and slicing-based photonic multiplication.
• The accelerator delivers application-tunable tradeoffs between precision, throughput, and energy, outperforming conventional FPGA and GPU devices for small- and medium-sized matrices.
• Its architecture integrates a tightly coupled digital–photonic design with on-chip buffers and adaptive precision control to mitigate analog noise and optimize high-speed computation.

LightMat-HP is a hybrid photonic–electronic accelerator designed to enable end-to-end, high-precision general matrix multiplication (GEMM) with configurable numerical formats. Matrix multiplication is a foundational operation in both large-scale artificial intelligence workloads and scientific computing; existing electronic accelerators are increasingly limited by constraints in memory bandwidth and energy efficiency. Leveraging the ultra-high bandwidth and parallelism of photonic computing, LightMat-HP overcomes the low-precision limitations of analog photonic devices by integrating block floating-point (BFP) arithmetic, a slicing-based photonic multiplication scheme, and a tile-based dataflow. The system achieves sustainable, application-tunable tradeoffs between precision, performance, and energy efficiency, outperforming conventional FPGA and GPU devices as well as photonic baselines such as BITLUME, particularly for small- and medium-sized matrices (Gong et al., 14 Apr 2026).

1. System Architecture

LightMat-HP employs a tightly coupled digital–photonic hybrid architecture, logically divided into digital and photonic subsystems. The digital subsystem manages external DRAM access, converts standard floating-point (FP) matrices to BFP format via FP2BFP units, and concatenates results for reconversion to FP (BFP2FP). Each photonic processing unit (PPU) includes a Mantissa Processing Unit (MPU) that decomposes high-bit-width mantissas into low-bit slices, digital-to-analog converters (DACs) driving Mach–Zehnder modulators (MZMs) for analog encoding, cascaded MZMs for parallel slice-wise photonic multiplication, wavelength-division multiplexing (WDM) demultiplexers and photodetectors for optical-to-electrical conversion, and high-speed analog-to-digital converters (ADCs) (Gong et al., 14 Apr 2026).

Key photonic device roles:

• MZMs encode digital values as analog optical intensities ($\propto \cos^2(\pi V/2V_\pi)$).
• WDM Photodetectors sum co-wavelength channels, realizing vector dot products via optical-power addition.
• Digital post-processing aligns and accumulates sub-products, maintaining full-precision in the electronic domain and containing analog noise.

2. Block Floating-Point (BFP) Arithmetic

BFP arithmetic underpins LightMat-HP's precision–performance tradeoffs. In BFP, a block of $N$ values $\mathbf{X} = \{x_1,\ldots,x_N\}$ shares a common exponent $e_s$ while each value maintains a $b$-bit mantissa $\hat{m}_i$. The transformation is defined by:

• $e_s = \lfloor \log_2(\max_i |x_i|) \rfloor - (b-1)$
• Mantissa scaling: $\tilde{m}_i = m_i \cdot 2^{e_s - e_i}$
• Quantization: $\hat{m}_i = Q(\tilde{m}_i)$, with $Q(\cdot)$ denoting rounding to $N$0 bits

Absolute quantization error per element is bounded by $N$1, and for a tile of size $N$2, total quantization error satisfies $N$3. Mantissa saturation prevents overflow/underflow (Gong et al., 14 Apr 2026).

3. Slicing-Based Photonic Multiplication Scheme

The analog photonic front-end is limited to 5–6 bits of linear precision by MZM non-idealities and noise. To enable high-precision GEMM, LightMat-HP slices each $N$4-bit mantissa into $N$5 sub-mantissas of width $N$6: $N$7 Photonic multiplication is performed in parallel for slice pairs; a PPU cycle emits four sub-products ($N$8, $N$9, $\mathbf{X} = \{x_1,\ldots,x_N\}$0, $\mathbf{X} = \{x_1,\ldots,x_N\}$1) via distinct wavelengths. Digital post-processing reconstructs the full product: $\mathbf{X} = \{x_1,\ldots,x_N\}$2 This digital accumulation constrains the propagation of analog noise to within a statistically bounded envelope: for a dot product of length $\mathbf{X} = \{x_1,\ldots,x_N\}$3, the RMS noise after exponent scaling satisfies

$\mathbf{X} = \{x_1,\ldots,x_N\}$4

where $\mathbf{X} = \{x_1,\ldots,x_N\}$5 is the standard deviation of Gaussian slice noise (Gong et al., 14 Apr 2026).

4. Tile-Based Dataflow for Large-Scale GEMM

Computing large GEMMs is achieved by partitioning the problem into $\mathbf{X} = \{x_1,\ldots,x_N\}$6 input/output tiles. Matrices $\mathbf{X} = \{x_1,\ldots,x_N\}$7 and $\mathbf{X} = \{x_1,\ldots,x_N\}$8 are sliced into $\mathbf{X} = \{x_1,\ldots,x_N\}$9 row-tiles and $e_s$0 column-tiles, respectively. Tile-level matrix blocks are flattened to vectors for sequential streaming into the PPU SRAM buffers. On-chip buffers (32 KB) and dual clock rates (256 MHz for data movement, 512 MHz for ADCs) support high-throughput burst operations, with algorithmic reconstructions aligning and concatenating outputs to form the final result matrix (Gong et al., 14 Apr 2026).

5. Precision–Performance Trade-offs

Adjusting BFP mantissa width ($e_s$1) and corresponding slice count $e_s$2 allows flexible control of GEMM error, throughput, and energy:

• $e_s$3: RelL$e_s$4 error $e_s$5 0.8%, throughput $e_s$6 4 TFLOPS, energy $e_s$7 25 TFLOPS/W
• $e_s$8: RelL$e_s$9 0.2%, throughput $b$0 6 TFLOPS, energy $b$1 32 TFLOPS/W
• $b$2: RelL$b$3, throughput $b$4 4 TFLOPS, energy $b$5 28 TFLOPS/W

These results delineate a Pareto frontier, enabling selection of application-appropriate precision at minimal computational cost (Gong et al., 14 Apr 2026).

6. Experimental Validation and Benchmarking

The prototype employs an AMD Zynq UltraScale+ RFSoC ZCU111 (14-bit DACs, 12-bit ADCs), tunable lasers at 1550 nm, Thorlabs 10 GHz MZMs, and 32 KB on-chip buffers per DAC player. The modulator region (ENOB $b$6 5 bits) dictates slice width.

Performance for 1024$b$71024 GEMM (FP32 output, BFP6+mantissa10) after 100 trials is summarized below:

Platform	Throughput (TFLOPS)	Latency (ms)	Energy (TFLOPS/W)	RelL$b$8 (%)
CPU (MKL)	0.12	450	0.10	0.00†
GPU (RTX3060)	6.00	9.5	39.4	0.00†
FPGA (ZCU111)	1.25	48	5.4	0.00†
BITLUME	3.90	15.4	26.0	0.08
LightMat-HP	6.65	8.1	39.1	0.15

† Exact FP32 result.

LightMat-HP achieves 1.5–2.5× lower latency than BITLUME and up to 5× lower latency than GPU/FPGA at small/medium matrix sizes, while matching or exceeding their energy efficiency (Gong et al., 14 Apr 2026).

7. Future Directions and Outlook

Proposed extensions include scaling LightMat-HP to chiplets and multi-chip photonic clusters via integrated optical interconnects, supporting trillion-element matrices, incorporation of on-board optical or phase-change memory (reducing DAC/ADC load), and adaptive precision scheduling to match per-tile and per-application error budgets. These directions are anticipated to further the integration of photonic hardware in high-precision workloads across AI and scientific applications, overcoming existing precision, bandwidth, and energy barriers in both electronic and photonic platforms (Gong et al., 14 Apr 2026).