Photonic Interconnect Overview

Updated 2 January 2026

Photonic interconnects are physical links that use guided optical or near-infrared waves to transmit digital and quantum information with high bandwidth and low energy consumption.
They integrate on-chip waveguides, modulators, and advanced coupling techniques to overcome limitations of traditional copper-based interconnects.
Applications span high-performance computing, data centers, AI hardware, and quantum networks, driving scalable and energy-efficient system architectures.

A photonic interconnect is a physical and architectural link that employs guided electromagnetic waves, typically in the optical or near-infrared range, to carry digital or quantum information between circuits, chips, boards, or multi-chip assemblies. Such interconnects exploit photonic integration—including on-chip waveguides, modulators, filters, detectors, and off-chip coupling—to deliver extremely high aggregate bandwidth, low energy-per-bit, and scalable spatial or spectral multiplexing. Photonic interconnects have emerged as essential enablers in applications spanning on-chip high-performance computing, chiplet-based system-in-package architectures, data-center composable memory, heterogeneously integrated photonics, artificial intelligence hardware, and modular quantum networks, addressing the scaling and efficiency limitations of copper-based electrical interconnects.

1. Physical Principles and Architectural Types

Photonic interconnects leverage various light-guiding and coupling mechanisms, which determine their loss, bandwidth, and integration compatibility:

On-chip waveguide links: Single-mode or multimode dielectric waveguides (silicon, silicon nitride, polymer) transfer signals on-chip or in 2.5D/3D interposer contexts, supporting advanced multiplexing via mode-division multiplexing (MDM, up to 2×100 Gb/s/mode with <7 dB insertion loss (Wu et al., 2017)) and dense wavelength-division multiplexing (DWDM) using microring or Mach-Zehnder modulators (Ding et al., 2014, Müller et al., 2015).
Off-chip and chip-to-chip coupling:
- Grating couplers (standard, apodized, or topological UGR): Optical antennas etched into the chip surface, enabling vertical coupling to fibers or between stacked chips. Unidirectional guided resonance couplers have achieved record-low loss (0.34 dB facet, 0.94 dB chip-to-chip) and >30 nm 1 dB bandwidth on SOI (Wang et al., 2023).
- Inverse taper edge couplers: Tapered waveguide transitions for butt-coupling to fibers or other chiplets, with optimized designs yielding <1 dB per interface.
- Photonic wire bonds (PWBs): Direct-write, freeform 3D polymer waveguides are “wire-bonded” in situ between chips, with <0.8 dB per interface and >300 nm bandwidth, supporting >5 Tbit/s aggregate data rates (Lindenmann et al., 2011).
- 3D-nanoprinted interposers: Passive, platform-agnostic mode converters (e.g., parabolic reflectors and fiber funnels) achieve 2.2 dB/facet I/O loss, 2.5 dB die-to-die loss, and 140 nm bandwidth, tolerant to ±4–6 µm misalignment (Huang et al., 2024).

In multi-chip assemblies or large-scale packages, interconnects must support high spatial density (hundreds of channels per mm²), wide spectral bandwidth, and interoperation among dissimilar material platforms (Si, InP, diamond, etc.).

2. Photonic Interconnects in Large-Scale Digital Systems

Photonic interconnects are foundational in the evolution of in-package and on-chip data movement:

On-chip/global routing (GLOW): Integer linear programming-based synthesis assigns photonic routes and wavelength channels with objectives of minimizing total optical power (modulator, detector, and ring-heater contributions), delay, and thermal drift per net. The joint optimization considers routing continuity, WDM channel capacity, insertion loss, delay constraints, and resonator thermal reliability, delivering up to 50% lower optical power versus greedy schemes, with full ISPD’07–08 benchmark demonstration (Ding et al., 2014).
Mode-division and wavelength-division multiplexed NoCs: Advanced modulation (OFDM/16-QAM), two-mode MDM, and integrated microring modulator/detector arrays demonstrate single-lane 2×100 Gb/s with 5–7 dB insertion loss, <0.93 dB crosstalk penalty, and net payloads >80 Gb/s/mode given FEC (Wu et al., 2017).
Panel-scale and wafer-scale photonic fabrics: Multi-layer SiN-based interposer platforms, e.g., up to 500 mm × 500 mm, integrate programmable crossbar switches and frequency-comb WDM sources, delivering >0.8 Tb/s/mm², >26 routes per tile, and >500 mm in-plane reach, with edge coupler and multi-modal packaging solutions (Hsueh et al., 8 Aug 2025, Kumar et al., 20 Jul 2025).
3D electronic-photonic vertical integration: Photonic Through-Silicon Optical Vias (TSOVs) enable vertical connectivity in chiplet stacks. Areal bandwidth densities >10 Tb/s/mm² are shown with per-link E/bit ≈100 fJ and <0.7 dB/TSOV coupling losses; 3D-EPIC platforms combine these with traditional TSVs for power delivery and ultra-low-latency electronics (Samanta et al., 4 Oct 2025).

Compression of energy-per-bit (down to <100 fJ/bit in optimal 3D-EPIC (Samanta et al., 4 Oct 2025) and monolithic GHz silicon photonic links (0907.0022)), bandwidth density, and latency directly result from the integration density and modularity of the photonic interconnect architecture.

3. Coupling Technologies and Loss/Performance Engineering

Optimizing the interface between photonic components is critical for performance and manufacturability:

Grating couplers (GCs and UGRs): Adiabatically-apodized or topological UGR GCs achieve <0.34 dB fiber-to-chip loss, >30 nm bandwidth, and high fabrication tolerance (±30 nm shifts yield <0.6 dB penalty) (Wang et al., 2023). Coupler designs co-optimize phase matching, apodized radiation profiles, and polarization purity for both vertical and interposer stacking applications.
Wirebond and 3D-printed interposers: Two-photon polymerization (TPP) enables freeform photonic waveguide “wire bonds” at picosecond writing speed, with insertion losses <1.6 dB (over 2 interfaces) and bandwidths exceeding 300 nm (Lindenmann et al., 2011). 3D-nanoprinting adds mode size conversion (e.g., 5:2 from SMF to SOI) and sub-micron mechanical accuracy to support chiplet integration of dissimilar platforms (e.g., Si/InP) (Huang et al., 2024).
Evanescent, alignment-free couplers: Engineered lateral and angular evanescent couplers demonstrate fundamentally relaxed alignment tolerances (Δθ >5°, Δr >10 μm), allowing universal connectors between photonic circuit boards and chiplets without sub-µm placement (Bandyopadhyay et al., 2021).
Insertion loss, bandwidth, density: Photonic wire bonds, 3D-printed interposers, and recent UGR designs all significantly outperform traditional grating and edge couplers in bandwidth-density-product and manufacturability; limitations primarily arise in mass production rate and environment-stability for polymer-based architectures.

A summary table of key coupling technologies:

Technology Type	Typical Insertion Loss	Bandwidth	Alignment Tolerance
Topological UGR GCs	0.34–0.94 dB	>30 nm	±30 nm
Photonic wire bond	0.8 dB/interface	>300 nm	±0.5 μm (auto-correct)
3D-nanoprinted interposer	2.2 dB/facet	140 nm	±4–6 μm
Edge/inverse taper	0.5–1 dB	>100 nm	<200 nm
Evanescent (AFPI)	<0.2 dB	180 nm	>5° / >10 μm

4. Photonic Interconnects for Quantum and Hybrid Systems

Quantum photonic interconnects are central to modular quantum processors, distributed entanglement networks, and optically mediated quantum memory architectures:

Quantum entanglement and coherent gate teleportation: Silicon photonic interconnects coherently convert between path and polarization encoding for fiber transmission, allowing on-chip-generated entanglement and two-qubit CNOT operation to be teleported between remote nodes over 5 m to 1 km fiber. Achieved average Bell-state fidelity is 95.69% (5 m) and 94.07% (1 km); gate process tomography yields 94.81% (5 m) and 93.04% (1 km) (Feng et al., 2024).
Diamond-based quantum interconnects: Wafer-scale diamond membrane transfer enables arrays of SiV-based quantum memories with spin–photon cooperativities up to 100, sub-dB fiber-device insertion loss, and deterministic integration onto silicon photonics and control electronics (Riedel et al., 8 Aug 2025).
Passive and modular chip-to-chip quantum links: Universal, passive 3D-printed and evanescent couplers enable chip-agnostic quantum photonic circuits (e.g., Si/InP, III–V/Si) without altering platform process, supporting die-to-die loss <2.5 dB and spectral ranges >140 nm (Huang et al., 2024).
Monolithic quantum interconnects: Bell-violation (S=2.638±0.039) is achieved between two Si photonic chips connected by 10 m fiber, chainable for multi-chip quantum networks (Wang et al., 2015).

Loss minimization and phase-stable coupling are critical to maintaining high-fidelity entanglement distribution and coherent gate operations over chip-to-chip photonic links.

5. System-Level Performance and Scalability

System architects leverage photonic interconnects to overcome critical bottlenecks in memory, data movement, and bandwidth scaling:

Bandwidth and energy scaling: Pathways combining low-loss waveguides (<1 dB/cm), wide free spectral range (MRR FSR ~80 nm), and elevated optical power budget (MAOP>15 dBm/channel) demonstrate >4 Tb/s per on-interposer link with energy/bit ≈0.2–1 pJ, supporting multi-Tb/s system-in-package designs (Karempudi et al., 2023, Karempudi et al., 2020).
Large-scale memory disaggregation: Optically Connected Memory (OCM) leverages MRR-based WDM to pool remote DRAM with 1.07 pJ/bit, ≤20 ns added latency, and 5.5× lower slowdown vs 40G PCIe-based architectures (Gonzalez et al., 2020).
Server- and rack-scale fabrics: Programmable photonic fabrics (Morphlux) use wafer-scale SiN meshes with MZI switches and per-tile WDM transceivers, offering up to 66% higher available bandwidth and 1.72× ML training throughput improvement (Kumar et al., 20 Jul 2025).
On-chip networks-of-chip (NoC): HERMES demonstrates scalable hierarchical architectures using adiabatic coupler–based butterfly broadcast and circuit-switched subnets, handling up to 1024 cores with linear local/domain power scaling and near-constant per-domain latency (<24 cycles) (Mohamed et al., 2014).
3D-integrated systems: 3D-EPIC platforms featuring TSOVs support arbitrary die stacking and vertical optical interconnect at >10 Tb/s/mm², <100 fJ/bit, and sub-ps conversion latency (Samanta et al., 4 Oct 2025).
Neural network applications: 3D polymer waveguide fractal interconnects scale photonic fan-out to >80 per coupler and enable massively parallel, low-footprint vector-matrix-product operations (Moughames et al., 2019).

The scalability of photonic interconnects is thus constrained by integrated device loss, power envelope, thermal management, and the coupling density supported by the interposer or package floorplan.

6. Future Challenges and Directions

Key challenges and prospective research avenues include:

Dynamic configurability and real-time adaptation: Achieving rapid reconfiguration of photonic fabrics to match runtime workload variability (e.g., AI in-package routing (Kumar et al., 20 Jul 2025)) and dynamic voltage/frequency scaling scenarios.
Thermal reliability and feedback: Nonlinear, coupled thermal models and feedback loops to stabilize microring resonator arrays, minimize drift, and manage cross-talk in high-density interposers (Ding et al., 2014).
Advanced forms of multiplexing: Expanding mode-division and spatial-division multiplexing, along with multidimensional WDM, to further scale aggregate interconnect density and exploit the modal diversity of new waveguide materials (Wu et al., 2017).
Heterogeneous integration: Standardizing passive, alignment-free interposers (TPP, 3D-print, evanescent) for robust, scalable packaging of Si, InP, LiNbO₃, and diamond-based photonics (Huang et al., 2024, Riedel et al., 8 Aug 2025, Bandyopadhyay et al., 2021).
Manufacturability and automation: Accelerating TPP/3D-print wire-bonding, developing closed-loop alignment, and process integration for high-yield, large-area, multi-chip photonic assemblies (Lindenmann et al., 2011, Huang et al., 2024).
Quantum-classical convergence: Integration of quantum memory, entanglement distribution, on-chip error correction, and classical photonic switch fabrics for scalable modular quantum computing (Feng et al., 2024, Riedel et al., 8 Aug 2025).

Photonic interconnects are thus positioned as an essential enabling substrate—spanning classical and quantum regimes—for future scalable computing, AI, disaggregated memory, and quantum network platforms.