Latency-Oriented Neural Network Learning

• Latency-oriented neural network learning comprises methods that treat latency as a key design and training variable rather than a post hoc metric.
• It leverages hardware-aware architecture search, differentiable latency predictors, and compression strategies to optimize accuracy under strict time budgets.
• These approaches enable ultra-low-latency performance in spiking networks, edge devices, and autonomous systems by integrating temporal coding and adaptive control.

Latency-oriented neural network learning is a class of methods in which latency is treated as a primary design, training, or control variable rather than as a post hoc deployment statistic. In the recent literature, the term spans several distinct but related regimes: hardware inference latency in neural architecture search and compression, end-to-end service delay in networked systems, temporal horizon in spiking neural networks, and spike-time or propagation-delay coding in biologically inspired models. Across these regimes, the shared objective is to learn representations, policies, or architectures that remain accurate, reliable, energy-efficient, or safe under an explicit temporal budget (Akhauri et al., 2024, Xu et al., 2022, Lu et al., 24 Mar 2026, Hao et al., 2024).

1. Problem formulations and latency metrics

A defining feature of this literature is that latency is formalized differently depending on the computational substrate and application. In hardware-aware neural architecture search, latency is the device-specific objective $l : \mathcal{A} \to \mathbb{R}$ mapping an architecture to a deployment metric such as latency, accuracy, or energy. In software-defined networking, end-to-end latency can be predicted indirectly by first estimating queue occupancy $\hat y$ and then computing link delay as $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$. In secure network slicing, latency is the sum of blockchain-management and service-provisioning delay, while reliability is modeled through a denial-of-service indicator. In spiking systems, latency is often the number of simulation steps, the first-spike time, or the timing alignment of presynaptic arrivals (Akhauri et al., 2024, Larrenie et al., 2023, Hao et al., 2024, Lu et al., 24 Mar 2026).

The secure network-slicing formulation is especially explicit. The optimization is

$$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$

where $a_i(t)$ is the compute resource allocated by base station $i$ in slot $t$, $\tau_i(t)$ is processing latency, and $c_i(t)$ is the instantaneous DoS indicator. Processing latency is defined as

$$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$

so latency is inversely related to allocated compute, while reliability is encoded by

$\hat y$0

This formulation makes latency-oriented learning a constrained decision problem rather than a pure prediction or classification problem (Hao et al., 2024).

A recurrent conclusion is that latency is not interchangeable with coarse complexity proxies. Several papers explicitly argue that FLOPs, per-layer lookup tables, or parameter counts can correlate poorly with real latency because latency depends on device microarchitecture, compiler and runtime behavior, operator interaction, memory access, input shape, batch size, and topology. This is the main reason latency-oriented learning repeatedly introduces learned latency predictors, differentiable surrogates, or hardware-customized measurement pipelines instead of relying on static complexity measures alone (Akhauri et al., 2024, Xu et al., 2020, Nasery et al., 2023).

2. Hardware-aware architecture search and latency-constrained model design

One major branch of the field embeds latency directly into architecture optimization. In latency-aware differentiable NAS, the search objective augments validation loss with a differentiable latency term,

$\hat y$1

where latency is defined as the expected latency of sampled sub-architectures and optimized with a straight-through estimator. The associated latency prediction module encodes DARTS cells as a 112-dimensional binary vector and uses a fully connected regressor with widths $\hat y$2. With 100K sampled architectures, the predictor reaches absolute/relative errors of $\hat y$3 ms and $\hat y$4 on GPU, and $\hat y$5 ms and $\hat y$6 on CPU. Search-time integration reduces latency by roughly $\hat y$7–$\hat y$8 while preserving accuracy; for example, on CIFAR-10, DARTS at $\hat y$9 ms becomes LA-DARTS at $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$0 ms, and PC-DARTS at $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$1 ms becomes LA-PC-DARTS at $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$2 ms (Xu et al., 2020).

A later predictor-centric NAS line studies latency transfer under difficult hardware shift. NASFLAT constructs benchmark tasks by partitioning devices with Spearman correlations and a Kernighan–Lin-style procedure into sets such as ND, N1–N4, NA and FD, F1–F4, FA, thereby forcing transfer to unseen and sometimes poorly correlated target devices. Its predictor combines a graph neural network over architecture graphs, hardware embeddings, operation-specific hardware modulation, supplementary encodings such as Arch2Vec, CATE, ZCP, and CAZ, and a pretrain-then-finetune strategy trained with pairwise hinge loss. The reported outcome is best performance on 11 of 12 few-shot latency prediction tasks, with a 22.5% average improvement and up to 87.6% on the hardest task, together with a $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$3 speedup in end-to-end hardware-aware NAS wall-clock time (Akhauri et al., 2024).

Compression-oriented work reformulates latency optimization as a single differentiable training run. The $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$4 latency-surrogate framework replaces discrete channel or rank counts with a scale-invariant surrogate and combines task loss with either FLOPs or an interpolated device-specific latency table. Its central form is

$\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$5

with a scale-invariant regularizer based on $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$6. The framework is applied to pruning, low-rank factorization, quantization, and their combinations. Reported results include a $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$7 reduction in FLOPs on BERT fine-tuning tasks with only a $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$8 drop in performance, and an $\hat d_n = \hat y_n \frac{\mathbb{E}(|P_n|)}{c_n}$9 reduction in on-device latency for MobileNetV3 on ImageNet-1K without drop in accuracy while requiring $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$0 less training compute than state-of-the-art compression techniques (Nasery et al., 2023).

Hard latency constraints on edge devices motivate a more explicit architecture-learning mechanism. Zerorized Batch Normalization uses BatchNorm scale parameters $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$1 as channel-importance indicators, periodically zeroes $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$2 and $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$3 below a threshold predicted to meet a target latency, and exploits optimizer momentum so zeroized parameters can recover during training. A hardware-customized BP neural latency predictor, with 16-12-1 neurons and activations $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$4, $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$5, and $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$6, estimates device latency with a reported average error of $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$7. On ImageNet-100, this framework reduces GoogLeNet from $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$8 ms to $$\min_{a_i(t)} \ \mathbb{E}[\tau_i(t)] \quad \text{s.t.} \quad \mathbb{E}[c_i(t)] \le \epsilon_{\max},$$9 ms on Jetson Nano with a $a_i(t)$0 accuracy reduction, or only $a_i(t)$1 drop when coupled with quantization; on Jetson TX2, it compresses VGG-19 from $a_i(t)$2 ms to $a_i(t)$3 ms with a $a_i(t)$4 accuracy gain, and scales GoogLeNet from $a_i(t)$5 ms up to the same $a_i(t)$6 ms budget with a $a_i(t)$7 gain (Huai et al., 8 Jul 2026).

A structurally simpler approach studies multipath neural networks by using one-shot NAS over differentiable membrane permeabilities, pruning to a chosen path count, and then fitting a regression model over sampled path counts to predict the accuracy–latency curve. In that setting, parameter count is treated as a practical latency proxy for architectures of similar type, and the reported prediction errors are small: MAE is $a_i(t)$8 on MNIST, $a_i(t)$9 on CIFAR10, and $i$0 on iWildCam2019, with high Pearson correlations for most settings (Amer et al., 2021).

3. Latency prediction as a learned model

A second branch studies latency prediction itself as the principal learning problem. In adaptive end-to-end latency prediction for networks, the model estimates queue occupancy from queue-theoretic features and then converts occupancy into link delay analytically. The linear model uses the engineered feature vector

$i$1

with

$i$2

while a Bernstein-polynomial variant reduces the problem to $i$3. Parameters are trained by minimizing regularized mean-square error and adapted online through sliding windows, exponential forgetting, LMS-style updates, or recursive inverse-correlation updates. On the generated OMNeT++ dataset, linear regression yields end-to-end latency MSE $i$4 and MAPE $i$5, while degree-8 Bernstein regression yields MSE $i$6 and MAPE $i$7. The computational contrast with GNN baselines is large: training is reported as less than 1 second for linear regression versus more than 8 hours for GNNs, and complete-network inference as about $i$8 s versus $i$9 s (Larrenie et al., 2023).

Module-wise inference-latency prediction generalizes this idea to adaptive DNN systems. A flexible framework trains multiple regression models per module type using self-generated datasets with three input categories: Sampling Parameters such as batch size and layer shape, Measurable Parameters such as available memory and utilization rate, and Inferable Parameters such as model weight count and input size. It evaluates MEDN, Random Forest, MLP, and Linear Regression on modules including convolution, batch normalization, pooling, linear layers, and composite blocks. MEDN, a Multi-task Encoder-Decoder Network with one encoder and two decoders for prediction and reconstruction, uses Smooth L1 losses and module-specific MLP dimensions. The framework then performs time/space-efficient auto-selection: it first filters models within a tolerance of the best accuracy, then within a tolerance of the best $t$0, and finally chooses the model minimizing time-per-sample or size. Relative to a MEDN-only scheme, this auto-selection improves overall accuracy by $t$1 and $t$2 by $t$3 (Shen et al., 2023).

These prediction frameworks establish an important distinction within latency-oriented learning. In architecture search and compression, latency prediction acts as a differentiable surrogate for an outer optimization. In adaptive networking and module-level deployment, latency prediction is itself the deployed model, used to monitor dynamic conditions, select optimization actions, or evaluate candidate configurations without executing the full system (Larrenie et al., 2023, Shen et al., 2023).

4. Ultra-low-latency spiking neural networks

The most technically concentrated latency-oriented work appears in spiking neural networks, where latency is often identified with the number of simulation steps. One influential strategy is temporal compression by iterative retraining. IIR-SNN begins with a directly encoded SNN trained at $t$4 and then retrains it through progressively smaller temporal budgets, such as $t$5, treating time-step reduction as temporal-domain compression. With VGG16, it reports top-1 accuracies of $t$6 on CIFAR-10, $t$7 on CIFAR-100, and $t$8 on ImageNet at a single time step, together with $t$9–$\tau_i(t)$0 reduced latency compared with prior SNNs and $\tau_i(t)$1–$\tau_i(t)$2 higher energy efficiency than standard DNNs (Chowdhury et al., 2021).

A complementary approach increases information capacity per time step. Multi-threshold LIF neurons allow a neuron to emit multiple spikes in one step according to

$\tau_i(t)$3

and training proceeds with surrogate derivatives tailored to the multi-threshold discontinuities. This yields $\tau_i(t)$4 on MNIST, $\tau_i(t)$5 on FashionMNIST, and $\tau_i(t)$6 mean accuracy on CIFAR10 with only two time steps; on CIFAR10, the paper reports a $\tau_i(t)$7 average improvement over previously reported direct-trained SNNs with fewer time steps (Xu et al., 2021).

Event-stream SNNs pursue the same objective by aggressively shortening the input horizon. A spatio-temporal compression block aggregates asynchronous events into only $\tau_i(t)$8 steps, a synaptic convolutional block smooths discrepancies between adjacent compressed steps, and a Parametric Multi-threshold LIF neuron adds learnable membrane retention. On N-MNIST the method achieves $\tau_i(t)$9 with 2 time steps in 50 epochs, on DVS128 Gesture $c_i(t)$0 at 5 steps, and on CIFAR10-DVS $c_i(t)$1 at 5 steps or $c_i(t)$2 at 10 steps. The paper explicitly notes the latency–accuracy trade-off: at very high compression, DVS128 Gesture falls to $c_i(t)$3 when only 2 time steps are used (Xu et al., 2022).

Minimum-latency training can also be pursued by enriching within-step computation rather than temporal recurrence. A one-step framework based on partitioned and dilated windows, multi-directional membrane-potential fusion, and a projection function

$c_i(t)$4

packs multiple effective accumulations into a single time step. It reports $c_i(t)$5 and $c_i(t)$6 top-1 accuracy on CIFAR100 for CNNs and RNNs, respectively, both at $c_i(t)$7, as well as energy figures of $c_i(t)$8 mJ for the CNN and $c_i(t)$9 mJ for the LSTM on CIFAR-10 (Yao et al., 2024).

Direct differentiation on spike representations offers a more analytical route to low latency. DSR replaces raw spike-train differentiation with gradients through a clamp-based spike representation mapping, learns per-layer spike thresholds, and introduces a firing hyperparameter $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$0 to reduce quantization error. It reports $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$1 on CIFAR-10, $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$2 on CIFAR-100, $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$3 on ImageNet, and $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$4 on DVS-CIFAR10, with 20 or 50 steps rather than the hundreds or thousands commonly required by ANN-to-SNN conversion. The same work reports that reducing CIFAR-10 from 20 to 5 steps causes less than a $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$5 drop in accuracy (Meng et al., 2022).

Binary-weight SNNs bring memory and latency optimization together. ALBSNN uses an Accuracy Loss Estimator to decide which layers to binarize, a three-block binary approximation

$$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$6

and a GAP layer to replace fully connected layers. In the one-time-step regime, the reported accuracies are $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$7 on Fashion-MNIST, $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$8 on CIFAR-10, and $$\tau_i(t)=\tau_{\text{bc},i}(t)+\tau_{\text{sp},i}(t)=\frac{f_{\text{bc},i}(t)+f_{\text{sp},i}(t)}{a_i(t)},$$9 on CIFAR-100, while storage is reduced by more than $\hat y$00 on CIFAR tasks (Xu et al., 2022).

Taken together, these methods show that ultra-low-latency SNN learning is not a single technique but a family of design principles: temporal compression, multi-spike neurons, richer within-step feature reuse, representation-level differentiation, and selective weight binarization. A plausible implication is that the dominant question is no longer whether SNNs can operate with very small time budgets, but which mechanism best preserves information when the temporal horizon becomes the central constraint.

5. Latency coding, propagation delays, and online or prospective learning

Latency-oriented learning is not limited to reducing step count; it also includes models in which time itself is the representational carrier. In deep latency coding for TTFS-style SNNs, inputs are first transformed by a learned feature extractor,

$\hat y$01

and then mapped to spike times by

$\hat y$02

Training uses backpropagation through time, a straight-through estimator for the encoder, relaxed hidden-layer multi-spike dynamics, and a Temporal Adaptive Decision loss

$\hat y$03

where $\hat y$04 is derived from entropy-based confidence. This framework reports $\hat y$05 on CIFAR-10 at $\hat y$06 timestep, $\hat y$07 on CIFAR-100 at $\hat y$08 timesteps, $\hat y$09 on Tiny-ImageNet at 4 timesteps, and $\hat y$10 on CIFAR10-DVS at 4 timesteps, together with energy estimates of $\hat y$11 mJ on CIFAR-10 and $\hat y$12 mJ on CIFAR-100 (Lu et al., 24 Mar 2026).

A more local timing-based perspective changes propagation delays instead of weights. In delay-plastic spiking networks, the synaptic delay $\hat y$13 is updated so that presynaptic spikes that causally contribute to a postsynaptic event arrive more tightly clustered around the mean causal arrival time, within a 10 ms pre-before-post window. Inputs are latency coded over $\hat y$14, weights are fixed homogeneous weight $\hat y$15, and decoding is based on polychronous group pattern clustering with 80% and 90% thresholds. In a three-layer feedforward Izhikevich RS network on resized MNIST digits, training improves classification accuracy and supports generalization to an unseen class; with the 80% threshold, accuracy on the unseen digit 2 reaches up to 64%, with mean accuracy 32% among networks that could separate it (Farner et al., 2022).

Online optimization under low-latency temporal constraints leads to another family of methods. OTTT derives an online-through-time gradient by replacing full temporal backpropagation with a recursively updated presynaptic trace,

$\hat y$16

and then using

$\hat y$17

The method uses instantaneous loss, constant memory cost agnostic to time steps, and a three-factor Hebbian form. Empirically it outperforms BPTT at low step counts, reaching $\hat y$18 on CIFAR-10 and $\hat y$19 on CIFAR-100 at 6 steps, $\hat y$20 on ImageNet at 6 steps, and $\hat y$21 on CIFAR10-DVS at 10 steps; on CIFAR-10, it reduces memory by about $\hat y$22–$\hat y$23 at 6 steps (Xiao et al., 2022).

An even broader theoretical generalization is Latent Equilibrium, which addresses slow physical neurons by introducing a prospective voltage

$\hat y$24

Here the neuron communicates a phase-advanced estimate of its own future membrane state, so inference becomes quasi-instantaneous and effectively independent of depth despite leaky continuous-time dynamics. The framework derives both neuron and synapse dynamics from a prospective energy function and interprets the resulting updates as a biologically plausible approximation of backpropagation. It achieves competitive benchmark performance, including $\hat y$25 test error on MNIST with fully connected networks and $\hat y$26 on MNIST with LeNet-5-style convolutional networks (Haider et al., 2021).

A frequent misconception in this area is that latency coding necessarily requires a strict single-spike constraint. The deep latency-coding framework explicitly relaxes hidden-layer single-spike behavior and argues that energy efficiency depends on both spike count and inference duration, not on sparsity alone. This suggests that the operative trade-off is not “single spike versus multiple spikes,” but rather whether additional hidden-layer activity reduces the number of required timesteps enough to lower total latency and energy (Lu et al., 24 Mar 2026).

6. System-level applications, edge inference, and recurring trade-offs

Latency-oriented learning also appears in domains where the learned object is a policy or system controller rather than a classifier. In blockchain-secured low-latency wireless network slicing, the resource-allocation problem is cast as a constrained MDP and solved by a primal-dual DDPG-style algorithm with one actor and two critics: a reward critic $\hat y$27 for latency and a cost critic $\hat y$28 for DoS probability. Feature engineering compresses the original queue-like state into a low-dimensional state containing normalized available compute and a normalized summary of remaining latency. Exploration uses Ornstein–Uhlenbeck noise, and dual updates increase the penalty when predicted cost exceeds the allowable DoS level. In simulation with 10 base stations, $\hat y$29 G CPU cycles/slot, $\hat y$30 G CPU cycles/slot, and $\hat y$31, the method achieves lower processing latency than unconstrained DDPG baselines while satisfying the DoS constraint, with training curves converging after about 15 episodes even under malicious base-station attacks (Hao et al., 2024).

On edge hardware, latency orientation often means optimizing single-stream response time rather than throughput. EdgeDRNN is a GRU accelerator for batch-size-1 inference on a MiniZed FPGA that combines a vector processing-element array with the DeltaGRU temporal-sparsity algorithm. By thresholding input and hidden-state deltas and skipping entire weight columns, it reduces off-chip memory access by up to $\hat y$32. For a 10 million-parameter 2-layer GRU-RNN with weights in DRAM, it reports mean latency $\hat y$33, effective throughput $\hat y$34 GOp/s, wall-plug power $\hat y$35 W, and latency comparable to a 92 W Nvidia 1080 GPU while outperforming Jetson Nano, Jetson TX2, and Intel Neural Compute Stick 2 by $\hat y$36 in latency (Gao et al., 2019).

Closed-loop control makes latency a safety variable rather than merely a deployment cost. In end-to-end autonomous driving, the stopping-distance model includes a latency term,

$\hat y$37

and the best latency–accuracy operating point varies with scene context and available compute. A multi-resolution ResNet-34-based driving policy with per-resolution batch normalization supports runtime switching between input scales, while resolution retargeting adapts a pretrained single-resolution policy without access to the original training set. In CARLA, latency has a nonlinear cliff: around 150 ms, route completion begins to collapse and collisions rise sharply. Under latency envelopes of $\hat y$38 ms and $\hat y$39 ms, an oracle resolution switcher retains 100% success and 0% collisions while reducing red-light violations from 42 to 15 and from 43 to 17, respectively, relative to fixed low-resolution baselines (Weng et al., 27 May 2026).

Across these applications, several recurring trade-offs are explicit. First, lower latency is not universally achieved by lower nominal complexity; device-specific execution and closed-loop timing can reverse the ranking induced by FLOPs or parameter counts. Second, high reliability or safety constraints can force solutions away from the latency minimum, as in constrained network slicing. Third, the optimal model may require either compression or expansion depending on the device budget, as shown by latency-constrained scaling on Jetson TX2. Fourth, in temporal neural systems, fewer spikes alone do not guarantee lower total cost; shorter duration can dominate spike sparsity. This suggests that latency-oriented neural network learning is best understood as a family of constrained optimization problems in which temporal budget, computational substrate, and task semantics are jointly learned rather than sequentially accommodated.