Latency Drag: Structural Performance Gaps

• Latency Drag is the gap between nominal and observed system performance, defined by hidden dependencies, burst effects, and delayed actuation.
• It manifests in diverse domains—from edge inference with memory clock issues to adversarial overload in object detection—highlighting its cross-domain impact.
• Quantification is achieved by benchmarking observed performance against ideal or physics-derived baselines, revealing actionable areas for system optimization.

Searching arXiv for the cited papers to ground the article in current literature. arxiv_search(query="Latency Drag (Kang, 15 Jun 2026) Beyond CPU-GPU Frequency Memory-Clock and Tail Effects in Edge Inference Latency Estimation", max_results=5) Searching arXiv for the edge inference paper. arxiv_search(query="(Kang, 15 Jun 2026)", max_results=5) Latency drag denotes performance degradation attributable to latency inflation relative to a feasible, expected, or ideal operating point. Across recent literature, the term is used for several technically distinct but structurally related phenomena: hidden control axes and tail effects in edge inference, adversarially induced post-processing overload in object detectors, the mismatch between slow planning and real-time control budgets in game agents, excess benchmark loss from delayed feedback in online decisions, performance penalties from globally conservative DRAM timing, latency inflation from performance-oblivious inter-domain routing, and the residual gap between observed Internet RTTs and the fiber-propagation baseline (Kang, 15 Jun 2026, Wang et al., 2024, Li et al., 23 Jun 2026, Yi, 17 Nov 2025, Chang et al., 2018, Lin et al., 2024, Martínez et al., 2023). In all of these uses, the central object is not merely mean delay, but a structured gap between nominal and realized performance that can accumulate through hidden dependencies, burstiness, stale decisions, or policy constraints.

1. Conceptual scope and formalizations

Several papers formalize latency drag by comparing observed behavior against a benchmark rather than by reporting raw latency alone. In edge inference, drag is conditional miss amplification near deadline cliffs; in online decisions, it is the additive degradation caused by delayed feedback and its interaction with order sensitivity; in Internet measurement, it is the gap from a physics-derived RTT baseline (Kang, 15 Jun 2026, Yi, 17 Nov 2025, Martínez et al., 2023).

Domain	Benchmark	Representative formulation
Edge ML inference	Aggregate miss rate at a fixed deadline	$$D = \frac{P(\text{miss}_{t+1} \mid \text{miss}_t)}{p}$$
Online decisions	Ideal benchmark loss $L_{\mathrm{ideal}}$	$$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$
Internet RTT analysis	Fiber-propagation RTT baseline	$$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$

This variety of definitions reflects domain-specific observables. In deadline-driven systems, drag is often a reliability or tail-risk object; in learning and control, it is an excess-loss decomposition; in communication systems, it is an inflation over a physical lower bound. A plausible implication is that latency drag is best understood as a family resemblance concept: each formulation isolates the performance gap created when a system’s operative assumptions omit a latency-relevant mechanism.

2. Hidden axes, burstiness, and actuation lag in edge inference

In edge ML inference, latency drag is defined as “the accumulation of latency inflation and risk that arises when hidden axes of the platform and tail phenomena are ignored in estimation and control.” On an NVIDIA Jetson Orin Nano Super, drag manifests along three coupled dimensions: the memory clock as a missing control axis, temporally clustered deadline misses, and DVFS actuation delays that defer when a chosen operating point takes effect. The measurements were performed on a platform with L4T R36.5, 6 × Cortex-A78AE, an Ampere iGPU, and 8 GB LPDDR5; four lockable EMC rates exist in practice: $\{204, 665.6, 2133, 3199\}$ MHz (Kang, 15 Jun 2026).

The first mechanism is EMC sensitivity outside CPU–GPU-only models. Across the realistic upper EMC range from 2133 to 3199 MHz, median latency shifts by +11% to +48% depending on workload, including +45% for the GEMV decode proxy, +18% for ViT, +12% for MobileNetV2, and +15.3% for SLM decode. The paper also reports a reproducible non-monotonic case: for an L2-resident compute kernel at the top GPU clock, lowering EMC from 3199 to 2133 MHz reduces median latency by approximately 9%, from 18.60 ms to 16.91 ms. A GPU-frequency estimator profiled under one power profile and deployed under another consequently underestimates latency by up to 32%, because its nominally frequency-independent term $b$ has hidden EMC dependence. A parametric extension such as $T = k/f_{\mathrm{gpu}} + m/f_{\mathrm{emc}} + b$ fails in three of four workloads, whereas per-EMC tabulation repairs most workloads.

The second mechanism is tail clustering near knife-edge deadline cliffs. At fixed clocks, 100k-cycle runs show tight distributions, with p99.99 within at most 10% of the median, yet post-hoc deadline-miss curves fall off a cliff of approximately 1 ms. For MobileNetV2 at EMC = 2133 MHz under contention, misses drop from 100% at 5.0 ms to 0.25–0.26% at 5.5 ms and to at most 0.002% at 6.0 ms. Misses are not independent: at an aggregate miss rate of 0.1%, the next cycle also misses with probability up to 74%, giving a drag factor of approximately $0.74 / 0.001 = 740\times$. Even uncontended runs reached $540\times$; across MobileNetV2 cells, $D$ ranged from 40 to 740, and for a GEMV decode proxy from 10 to 50. Gaussian $L_{\mathrm{ideal}}$0 margins overshoot a 0.1% miss target by 13×–29×, whereas out-of-sample generalized Pareto margins stay within approximately 2× of that target across all eight configurations.

The third mechanism is actuation delay. Per-domain transition stalls remain below 100 $L_{\mathrm{ideal}}$1s at p95, but the new operating point takes approximately 1 ms for CPU, 5 ms for GPU, and 8 ms for EMC to take effect. During that lag, execution continues at the old frequency, so per-inference DVFS decisions frequently take effect only after the critical inference has already run. The paper therefore recommends EMC as a first-class axis in estimators, GPD-based rather than Gaussian deadline margins, conditional-miss modeling or weakly-hard constraints for burst risk, and explicit modeling of 1/5/8 ms actuation delays in horizon-aware control loops.

3. Adversarial post-processing overload in object detection

In NMS-based object detectors, latency drag is the system-level consequence of latency attacks: adversarial inputs inflate the number of candidate detections, forcing the post-processing pipeline into its worst-case regime and degrading throughput while increasing per-frame latency. The attack surface differs from standard misclassification or mislocalization attacks because the model’s outputs can remain largely correct while the time to deliver them exceeds real-time budgets. The relevant decomposition is

$L_{\mathrm{ideal}}$2

with $L_{\mathrm{ideal}}$3 dominated by NMS under attack. The paper models NMS time as piecewise in the candidate count $L_{\mathrm{ideal}}$4:

$L_{\mathrm{ideal}}$5

and also gives

$L_{\mathrm{ideal}}$6

where $L_{\mathrm{ideal}}$7 is IoU computation throughput and $L_{\mathrm{ideal}}$8 is effective CPU–GPU bandwidth. This makes latency drag explicitly hardware-dependent: embedded GPUs are reported as compute-bound under attack, whereas desktop and cloud GPUs become memory-bound because GPU–CPU transfers and CPU-side logic dominate (Wang et al., 2024).

The attack objective maximizes box confidence while minimizing box sizes so that more phantom boxes survive confidence filters and fewer are suppressed by IoU. This drives NMS into a quadratic regime, elevates synchronization overhead, and can induce cascading failure in downstream real-time tasks. The threat model used for training instantiates K-step PGD with $L_{\mathrm{ideal}}$9, $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$0 perturbations, and $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$1.

The proposed defense, Underload, is hardware-adaptive and background-attentive. Its rationale is that objectness loss is an effective proxy for latency attack behavior: perturbations generated by maximizing objectness loss have cosine similarity approximately 0.875–0.95 with perturbations from latency attack objectives, whereas classification loss correlates weakly. The method focuses inner maximization on background regions with a binary mask, shrinks the mask progressively, and stops when the expected candidate count meets a hardware capacity bound derived from $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$2, $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$3, and the post-processing budget. The paper evaluates YOLOv3, YOLOv5, and YOLOv8 on PASCAL-VOC, MS-COCO, and BDD100K across Jetson Xavier NX, Jetson Orin NX, RTX 4070 Ti Super, and A100. It reports that Underload restores real-time processing capability from 13 FPS to 43 FPS on Jetson Orin NX, with processing times returning to approximately 13–23 ms across YOLOv3/5/8. The same study also emphasizes that changing NMS variants or applying proposal caps can help but does not remove the root cause, namely adversarial inflation of background objectness.

4. Slow–fast mismatch in real-time agents

For real-time game agents and general computer-use agents, latency drag arises when a high-quality but slow planner cannot meet the timing budget of the perception–action loop. The control loop budget is written as $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$4; in the evaluated Atari setup, the environment runs at 60 Hz, the agent acts at approximately 15 Hz, and the per-tick budget is therefore approximately 66.7 ms. Against that budget, the reactive VLM MiniCPM-o 4.5 answers in milliseconds, with a warm-path latency of approximately 33 ms, whereas the reasoning VLM Qwen3-VL-8B-Thinking requires approximately 1.5 s per emission and is therefore unusable as a blocking controller (Li et al., 23 Jun 2026).

The proposed mitigation is a two-model architecture with asynchronous slow guidance. Two frozen VLMs of matched scale are coupled: a 9B reactive model closes the loop synchronously, while an 8B reasoning model emits at approximately 1 Hz and never blocks the loop. The standard coupling is a Text Bridge, in which the slow model’s full text emission, with median length 302 characters, is appended as a prompt suffix. The paper introduces a Latent Bridge as a continuous alternative: residuals from layer 24 of 36 in the slow model are projected into the fast model’s input-embedding space and prepended as 8 tokens of 4096 dimensions each, so that all 36 LLM layers can attend to them through standard causal attention. The bridge is the sole trained component, implemented as a 33 M-parameter 2-layer MLP with LayerNorm and GELU. An earlier cross-attention design converged offline with KL approximately 0.004 but failed in deployment; the prepend-style latent channel worked in deployment and was trained by minimizing action-distribution KL to the Text-Bridge policy, reaching final KL approximately 0.005 across games.

Latency accounting is central to the method. With vision caching, the warm-path latency of Fast-Only is approximately 33 ms, and the Latent Bridge is approximately 38 ms, with the 8 prepended latent tokens adding about 5 ms. Slow emissions are reused for roughly 15 ticks until the next update, so the system explicitly trades staleness against control-loop feasibility. The principal empirical result is that the Latent Bridge matches or beats the Text Bridge in every tested domain across seven Atari games and MetaDrive, significantly improving MsPacman by +57% and RoadRunner by +28% over Text. At the same time, combining both channels interferes destructively, with RoadRunner decreasing by 96%, and MetaDrive is a controlled negative: the Text Bridge adds no value and the Latent Bridge is demonstrably inert. The paper’s operational rule is correspondingly sharp: bridging helps if and only if slow reasoning already beats fast reaction, with $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$5 and $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$6 gains moving together at Pearson $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$7.

5. Delayed feedback and noncommutative online decisions

In online decision systems, latency drag is formalized as the excess benchmark loss caused by delayed feedback together with its interaction with order sensitivity. The paper defines loss using a Bregman divergence benchmark induced by a Legendre potential $$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$8:

$$\mathrm{Latency\ Drag}(\lambda;\varepsilon_\star) := g_1(\lambda) + g_{12}(\lambda,\varepsilon_\star)$$9

where $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$0 is the Bayes-optimal predictive object and $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$1. The master inequality is

$$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$2

where $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$3 is the latency penalty, $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$4 the order-sensitivity penalty, $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$5 their interaction, and $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$6 the nonconvexity or approximation penalty. In the paper’s own shorthand, latency drag is the additive component

$$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$7

Under convex Legendre assumptions, $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$8 and the decomposition is cleanly additive (Yi, 17 Nov 2025).

The geometry is projection-based. Order constraints define a feasible set $$\Delta = \mathrm{RTT}_{\text{observed}} - \mathrm{RTT}_{\text{baseline}}$$9, latency constraints define $\{204, 665.6, 2133, 3199\}$0, and sequential Bregman projections generate the penalties. The interaction term vanishes if and only if the constraint projections commute. This gives latency drag a precise geometric meaning: delayed feedback restricts measurability to pre-verification $\{204, 665.6, 2133, 3199\}$1-algebras, while noncommutative dynamics make the order in which constraints are enforced consequential.

The same paper gives an operational estimation procedure through a $\{204, 665.6, 2133, 3199\}$2 randomized design. Four regimes are constructed by toggling latency and order constraints: unconstrained, order-only, latency-only, and both. The sequentially aligned estimators are

$\{204, 665.6, 2133, 3199\}$3

with finite-sample clipping $\{204, 665.6, 2133, 3199\}$4. The empirical program is explicitly tied to streaming diagnostics such as effective sample size, clipping rate, and interaction heatmaps, using DR/IPW for selection and IPCW for censoring. This makes latency drag not merely a theoretical penalty but a measurable object that can be monitored and stress-tested under realistic deployment conditions.

6. Memory timing, routing policy, and end-to-end path inflation

At the hardware level, one use of latency drag refers to the performance penalty imposed by conservative DRAM timing. Flexible-Latency DRAM characterizes 240 DDR3 DRAM chips from three major vendors and shows substantial intra-chip and inter-chip variation in the safe latencies of activation, precharge, and restoration. Vendor-wide settings such as $\{204, 665.6, 2133, 3199\}$5 and $\{204, 665.6, 2133, 3199\}$6 at approximately 13.125 ns are chosen for the slowest cells, but many regions operate correctly at 10 ns, and large fractions of memory can run at 7.5 ns. Because slower cells are spatially clustered, FLY-DRAM stores a latency map and applies reduced timings to fast regions while retaining conservative timings for slow ones. In a simulated 8-core system, the reported average performance improvements are 13.3%, 17.6%, and 19.5% for the three vendors’ real chips (Chang et al., 2018).

At the routing layer, latency drag is defined as latency inflation caused by performance-oblivious inter-domain routing, especially BGP’s policy-first path selection. The mechanisms identified are circuitous routing, hot-potato early exit, and local-preference policies that favor economic relationships over RTT. The proposed response is standards-compatible rather than protocol-replacing: latency-proportional AS prepending encodes coarse latency into AS-path length via quantized prepends, while local preference neutralization equalizes import preference for selected premium prefixes. On an Internet-scale simulation with 58,604 ASes, the 90th-percentile one-way latency decreases from 113 ms under baseline BGP to 78 ms with ASPrep at $\{204, 665.6, 2133, 3199\}$7 ms, a 31% reduction, while total update messages rise from $\{204, 665.6, 2133, 3199\}$8 to $\{204, 665.6, 2133, 3199\}$9 (Lin et al., 2024).

At Internet-wide measurement scale, latency drag is the gap between observed RTT and the theoretical propagation baseline in optical fiber. Using more than 9 million ICMP RTT measurements between more than 100 globally distributed probes from 2014 to 2022, the paper fits regional regressions of RTT against geodesic distance and compares them with the baseline line of approximately 0.01 ms/km RTT. The reported 2022 regressions are approximately $b$0 for North America, $b$1 for Europe, and $b$2 for Africa. The study also reports a 39% average RTT reduction in PacificC over eight years, 16% in Europe, and 17% in North America, while emphasizing that capacity upgrades alone do not remove path stretch, fixed overheads, or routing detours (Martínez et al., 2023).

7. Cross-domain themes, misconceptions, and significance

Taken together, these studies suggest that latency drag is rarely a single-delay phenomenon. It is produced by omitted control variables such as EMC, algorithmic worst-case transitions such as NMS moving into a quadratic regime, stale planner outputs reused across multiple control ticks, geometric penalties from delayed feedback under noncommutative dynamics, globally conservative timing parameters that protect the slowest DRAM cells, routing policies that encode economics rather than latency, and end-to-end paths whose slope and intercept remain above the fiber baseline (Kang, 15 Jun 2026, Wang et al., 2024, Li et al., 23 Jun 2026, Yi, 17 Nov 2025, Chang et al., 2018, Lin et al., 2024, Martínez et al., 2023).

A recurring misconception is that latency drag is exhausted by average latency. The edge-inference results show that tight distributions can still produce deadline cliffs and bursty misses; the online-decision framework separates pure latency effects from interaction effects; and the Internet RTT analysis distinguishes fixed overheads from distance-dependent inflation. Another misconception is that more compute alone removes drag. The object-detection study shows that A100-class hardware remains vulnerable when post-processing and I/O become memory-bound; the Orin Nano study shows that higher GPU frequency does not subsume EMC; the game-agent study shows that a more capable slow model can be inert or harmful if it does not actually outperform the fast loop on the target domain; and the routing study shows that capacity upgrades do not eliminate policy-induced detours.

The literature converges on a different operational lesson. Hidden axes need explicit profiling or tabulation; tail behavior needs models that survive out-of-sample validation; asynchronous systems need horizon-aware gating rather than synchronous wishful thinking; and baseline-relative metrics are essential because drag is defined by the gap between a system’s nominal model and the actual constraints under which it runs. In that sense, latency drag functions as a unifying analytical object for reasoning about when latency becomes not merely a scalar cost, but a source of structural performance distortion.