EdgeDRNN: GRU Accelerator & Graph Generation

• The paper presents a GRU-based accelerator that exploits temporal sparsity via delta encoding to reduce DRAM accesses by up to 10×, enabling low-latency edge inference.
• EdgeDRNN also encompasses a sequential graph generative model that uses dual GRU RNNs to generate graphs with high novelty and rapid sampling compared to previous methods.
• The framework demonstrates practical applications from robotic prosthesis control to efficient graph generation, achieving energy efficiencies of up to 8.8 GOp/s/W on resource-constrained hardware.

EdgeDRNN denotes two distinct but widely-cited frameworks: (1) a family of FPGA-oriented GRU-based recurrent neural network (RNN) hardware accelerators exploiting temporal sparsity for low-power, low-latency edge inference, and (2) an edge-sequential graph generative model using dual-GRU RNNs. The first sense dominates device and embedded-AI literature, while the second appears in contemporary generative modeling research. Both are referenced by name in their respective original works (Gao et al., 2020, Gao et al., 2019, Gao et al., 2020, Bacciu et al., 2020). Each is treated separately below for clarity.

1. Temporal-Sparsity GRU Accelerator: Hardware Architecture and Dataflow

EdgeDRNN, as developed in (Gao et al., 2020, Gao et al., 2019, Gao et al., 2020), is a GRU-based RNN accelerator designed for edge devices (e.g., IoT, robotics, prosthetics) operating on resource-constrained FPGAs such as Xilinx Zynq-7007S. The architecture comprises:

• DRAM interface (AXI HP, 64-bit, up to 1 GB/s DDR3-L),
• Controller and Datamover for on-demand weight column loading,
• Delta Unit for detecting state/input changes (“deltas”) using configurable thresholds,
• D-FIFO for sparse value/column queuing,
• Processing Element (PE) Array (typically K=8 parallel MACs) for sparse multiply-accumulate,
• On-chip buffer memories (BRAM for $\hat{x}, \hat{h}$, partial sums),
• Output buffer for newly computed $h_t$.

The computation flows as: input/hidden-state deltas exceeding the given thresholds trigger sparse weight fetches from DRAM, where only relevant columns are transferred and processed. These MACs are accumulated and passed through a pipelined nonlinearity unit for GRU gate computation. The architecture is optimized for batch size 1, enabling low-latency, real-time operation.

2. Delta Network Algorithm and Temporal Sparsity Exploitation

The core algorithmic innovation is the “DeltaGRU” model exploiting temporal sparsity under the observation that, in many real-world streams, a majority of activations change little between timesteps. The delta encoding for input $x$ and hidden state $h$ at layer $l$ and element $i$ or $j$ is:

$$\hat{x}_{i,t} = \begin{cases} x_{i,t}, & |x_{i,t} - \hat{x}_{i,t-1}| \ge \Theta_x,\ \hat{x}_{i,t-1}, & \text{otherwise}, \end{cases} \quad \Delta x_{i,t} = \begin{cases} x_{i,t} - \hat{x}_{i,t-1}, & |x_{i,t}-\hat{x}_{i,t-1}|\ge\Theta_x,\ 0, & \text{otherwise}, \end{cases}$$

with analogous definitions for hidden state $\hat{h}_{j,t}$ and $\Delta h_{j,t}$ (Eqs. 1a–1d in (Gao et al., 2020)).

The DeltaGRU update is then accumulated in “delta memory” vectors $h_t$0:

• $h_t$1
• $h_t$2
• $h_t$3
• $h_t$4

Nonlinearities are then applied as in standard GRU (Eqs. 2e–2h).

A “temporal sparsity metric” (Eq. 3) combines layer-wise sparsities $h_t$5, $h_t$6 to yield effective sparsity $h_t$7, which directly determines the reduction in DRAM accesses as only nonzero delta columns are streamed and processed. For networks exhibiting $h_t$8 effective sparsity, off-chip memory traffic and MAC activity are reduced by approximately $h_t$9.

3. Hardware Implementation, Quantization, and Resource Utilization

EdgeDRNN is typically realized on the Xilinx Zynq-7007S MiniZed, utilizing only 8 DSPs for MACs, with all weights stored off-chip in quantized (INT8) DRAM format. Key aspects:

• PE array: K=8 parallel engines fully leveraging the 64-bit DRAM bandwidth.
• On-chip memory: state and partial sums in small BRAM banks; activation/partial sums in signed 16-bit.
• Control: thresholding and MAC assignment via finite-state machines; handshaking over AXI-Lite for configuration.
• Quantization: 8-bit weights, 16-bit activations, nominal accuracy loss ≤5% in L1 compared to floating-point, as demonstrated in prosthesis control experiments (Gao et al., 2020).
• Energy: At 100–125 MHz, system (PL+DRAM+PS) draws ~2.0–2.4 W with O(10^7) parameter models.

Measured resource utilization (MiniZed, (Gao et al., 2020)):

Resource	Available	Used by EdgeDRNN	% Util.
LUT	14,400	4,438	30.8%
BRAM	50	16 blocks	32%
DSP	66	9	13.6%

4. Performance Metrics and Energy-Efficiency Trade-Offs

Empirical results on 5–10 M-parameter 2-layer GRUs (Gao et al., 2020, Gao et al., 2019):

• Batch-1 mean latency: ~0.5 ms per timestep (e.g., 0.536 ms for TIDIGITS, H=768, $x$0).
• Effective throughput: 20.2 GOp/s.
• Wall-plug power: 2.3–2.4 W.
• System power efficiency: 7–8.8 GOp/s/W.

Comparative performance (representative, (Gao et al., 2020)):

Platform	Throughput (GOp/s)	Power (W)	GOp/s/W
EdgeDRNN	20.2	2.3	8.8
NVIDIA 1080 (FP16)	22.3	~82	~0.27
Jetson TX2	4.0	~8.1	0.49
Jetson Nano	2.5	~7.1	0.35
Intel NCS2 (FP16)	3.0	1.7	1.8

An accuracy–latency trade-off is parameterized by the delta threshold $x$1; increasing $x$2 magnifies effective sparsity (and thus throughput/energy savings) but increases prediction error (e.g., WER). Empirical sweep ((Gao et al., 2020), Table):

$x$3 (Q8.8)	$x$4 threshold	$x$5	Latency (µs)	Throughput (GOp/s)	WER (%)
0	0	46%	1344	8.0	0.7
64	0.25	90%	536	20.2	1.3

5. Applications: Real-Time Embedded RNN Inference and Control

Demonstrated use cases include:

• Spoken digit recognition (Gao et al., 2020, Gao et al., 2019): Large GRUs for voice datasets, attaining GPU-class latency at orders-of-magnitude lower power draw.
• Real-time robotic prosthesis control (Gao et al., 2020): Behavioral cloning for a powered transfemoral prosthesis (AMPRO3), with the accelerator achieving a $x$6 speedup over real-time. The complete prosthesis control loop (sensor-to-actuator) operates within a 5 ms budget, with EdgeDRNN inference occupying ≈ 20 µs and maintaining L1 loss within 5% of full-precision GRUs. All weights reside in off-chip DDR3L; on-chip memories buffer activations and memory vectors.

A plausible implication is that such architectures can support increasingly complex, adaptive controllers on affordable hardware, spanning a spectrum from IoT inference to closed-loop robotic actuation.

6. EdgeDRNN for Sequential Graph Generation

In a distinct but similarly named model, EdgeDRNN refers to a generative process for graphs via edge-wise sequential modeling with dual GRUs (Bacciu et al., 2020). The method proceeds by imposing a node order (static BFS yields optimal results), lexicographically sequencing edges, and modeling the process as two RNNs:

• RNN1 (first endpoint): Autoregressively generates source vertex sequence.
• RNN2 (second endpoint): Given source, predicts destination vertex, conditioned on RNN1’s final hidden state.

Loss is the sum of two cross-entropy terms (one for each sequence). Evaluation across five datasets (Ladders, Community, Ego, Enzymes, Protein) demonstrates that EdgeDRNN achieves high novelty (@K ≈ 0.99), uniqueness (0.90–1.0), and low KLD divergence in structural statistics—outperforming GraphRNN in sampling speed (by >2×) and retaining comparable sample quality.

Metric	EdgeDRNN	GraphRNN
Novelty@5K	≈ 0.99	≈ 0.99
Uniqueness@5K	0.90–1.00	0.90–1.00
Sampling time (5K)	3–9 min	17–52 min
Mean rank (KLD)	1.4–2.0	2.0–2.4

A key finding is that fixing BFS node order yields optimal generalization/performance. Dynamic or SMILES-based orderings degrade both train loss and output diversity.

7. Practical Considerations and General Guidelines

For edge RNN accelerators:

• Exploit temporal sparsity for low-batch, time-series workloads.
• Quantize aggressively while retraining for negligible accuracy loss.
• Tune PE count to saturate DRAM bandwidth; match off-chip/on-chip bus widths.
• Employ runtime-configurable thresholds to trade off accuracy/performance.
• Minimize on-chip BRAM/DSP utilization; offload bulk weights to DRAM.

For sequential graph generation:

• Use static BFS node ordering for stability and diversity.
• Employ dual-RNN architectures for conditional edge/index prediction.
• Evaluate using both novelty/uniqueness and higher-order statistics (degree, clustering, motif counts).

EdgeDRNN, both as RNN accelerator and as a graph generative model, exemplifies the value of targeted architectural and algorithmic design in resource-constrained and sequential data contexts (Gao et al., 2020, Gao et al., 2019, Gao et al., 2020, Bacciu et al., 2020).