P-Type Silicon Detector Arrays

• P-type silicon detector arrays are large-area, segmented semiconductor devices built on p-doped substrates for precise charged particle, photon, and electromagnetic shower detection.
• They employ advanced techniques such as photolithography, ion implantation, and thermal annealing to optimize charge collection efficiency, radiation hardness, and time resolution.
• Systematic electrical characterization via IV and CV measurements confirms uniform full depletion and controlled breakdown, making them suitable for high granularity calorimetry and nuclear applications.

P-type silicon detector arrays are large-area, segmented devices built on high-resistivity p-type silicon substrates for precision charged particle, photon, and electromagnetic shower detection across high-energy physics, nuclear physics, X-ray diagnostics, and photon-counting applications. P-type refers to the substrate or bulk region being doped with acceptors (typically boron) to create a semiconductor where holes are the majority carriers. Contemporary p-type arrays are fabricated using advanced techniques to optimize charge collection efficiency, radiation hardness, segmentation, and time resolution, with device concepts ranging from pad arrays to pixel detectors and specialized architectures such as vertical nanopillar photodiodes.

1. Silicon Substrate Preparation and Array Fabrication

The fabrication workflow for p-type silicon detector arrays centers on the use of high-resistivity p-type wafers, typically 6- or 8-inch diameter, with epitaxial thicknesses ranging from 50 μm up to 300 μm for varying signal and radiation tolerance needs (Sawan et al., 8 Aug 2025, Kałuzińska et al., 3 Mar 2025, Villani et al., 26 Jun 2024). Key process steps include:

• Thermal oxidation and photolithography: Field oxide (e.g., 3500 Å) is grown after surface cleaning and sacrificial oxidation. Photolithographic patterning defines the active regions, guard rings, and isolation regions.
• Ion implantation: Both phosphorus (n⁺) for active pads/pixels/guard rings and boron (p⁺) for isolation between pads, with critical gaps (e.g., 60 μm between pads) set by mask alignment.
• Annealing (drive-in): Long-duration annealing ensures activation and control of junction depth in both active and guard ring implants.
• Passivation and metallization: A passivation layer (e.g., 3000 Å LPCVD oxide) is deposited, openings are etched, and 1 μm aluminum contacts are formed and patterned (with metal overhang designs to minimize surface leakage). Sintering at elevated temperatures (e.g., 440 ° C in nitrogen) finalizes the process.
• Advanced layouts: Vertically aligned nanostructures as in CNT-Si p-i-n arrays (Ahnood et al., 21 Jun 2024) represent a further innovation, exploiting template-assisted deposition for enhanced electric fields and light trapping.

Fabrication variations include hexagonal pad layouts for high-granularity calorimetry (Kałuzińska et al., 3 Mar 2025), segmented 8×9 pad arrays (Sawan et al., 8 Aug 2025), and deep-trench edgeless planar pixels (Calderini et al., 2013, Bomben et al., 2016).

2. Electrical Characterization and Full Depletion

Systematic characterization involves both current–voltage (IV) and capacitance–voltage (CV) measurements:

• IV testing: Reverse bias voltage sweeps (up to 700 V) yield leakage currents (typically <50 nA/cm² for >90% of large arrays (Sawan et al., 8 Aug 2025)), with measured breakdown voltages of 450–700 V (TCAD simulations often predict higher, e.g., >1400 V, implying fabrication-induced defect sensitivity).
• CV testing: Extraction of full depletion voltage (FDV) from the 1/C² vs voltage curve, typically saturating in the 90–150 V range (alignment with TCAD predictions near 160–170 V is observed).
• Device uniformity: Across all pads, both FDV and breakdown voltage distributions are tight, confirming process control.

The depletion criterion is routinely checked via:

$$1/C^2(V) \text{ saturates for } V \geq V_\text{FDV}$$

This ensures complete extension of the depletion region and thus optimal charge collection.

3. Performance in Particle and Shower Detection

Laboratory and test beam measurements assess charge collection, signal-to-noise, and spatial uniformity:

• Minimum Ionizing Particle (MIP) signal: Clear separation from pedestal with S/N ratios above 5.5 (up to ~6.1) when exposed to ⁹⁰Sr β sources or 10 GeV pions at CERN PS (Sawan et al., 8 Aug 2025). Landau–Gaussian fits to the charge spectrum confirm MIP response.
• Uniformity and saturation: Voltage scans demonstrate MPV separation saturates above FDV, indicating full depletion over the array; position scans show uniform pad response.
• Electromagnetic shower profiling: With incident positron beams and variable tungsten absorbers (each 3.5 mm ≈ 1 X₀), the longitudinal shower profile and cluster size are quantified. The shower maximum position increases with incident energy (e.g., 3.9 X₀ → 4.6 X₀, 2 GeV → 4 GeV), and profiles match Geant4 simulations.
• Array segmentation: Dense 8×9 pad layouts enable fine spatial sampling; integration with advanced ASICs (HGCROC) provides robust data acquisition.

These performance metrics support deployment in environments requiring electromagnetic and hadronic calorimetry (e.g., ALICE FoCal upgrade) (Sawan et al., 8 Aug 2025, Kałuzińska et al., 3 Mar 2025).

4. Inter-pad Isolation, Guard Ring Engineering, and Optimization

Critical to large arrays are edge isolation and breakdown management:

• Edge isolation: Inter-pad regions utilize p-type (boron) implantation; guard rings flank active arrays, with 2–3 rings optimizing leakage and breakdown (Villani et al., 26 Jun 2024, Sawan et al., 8 Aug 2025).
• Implant dose optimization: P-spray (uniform) or p-stop (floating island) approaches enhance n⁺ strip isolation, as electron accumulation from fixed positive oxide charge can otherwise short adjacent strips (Saxena et al., 2020). Simulations indicate only high implant doses suffice for isolation at post-irradiation oxide charge levels (Q_F ≈ 2×10¹² cm⁻²), but excessive dose increases local electric field, reducing breakdown voltage (V_BD may drop to 150–400 V). Medium doses appropriately balance isolation with breakdown reliability.
• Breakdown mitigation: Guard rings with oxide isolation or subsurface p-stop limit surface inversion and improve leakage current profiles.

These design choices address both initial electronic performance and radiation-induced degradation scenarios.

5. Radiation Hardness, Charge Collection, and Annealing Dynamics

P-type silicon arrays are engineered for sustained performance under high fluences (up to 1.5×10¹⁶ n_eq/cm²) (Kałuzińska et al., 3 Mar 2025, Spiegel et al., 2010), with comprehensive studies on:

• Charge collection under irradiation: TCT measurements quantify collected charge via transient currents from laser excitation. For instance, thicker diodes (300 μm) deliver higher initial signal but incur more rapid degradation than thinner diodes (120–200 μm), which maintain near-100% collection at highest fluences (Kałuzińska et al., 3 Mar 2025).
• Annealing behavior: Isothermal annealing at 60 °C leads to an initial recovery of charge collection followed by reverse annealing. The optimal duration depends on device thickness and fluence, with laboratory and in-reactor annealing effects accounted for via the Hamburg model.
• Design impact: The observed annealing curves have led to an update in sensor deployment within HGCAL: thicker sensors now used up to 1.7×10¹⁵ n_eq/cm², thinner sensors above this threshold (Kałuzińska et al., 3 Mar 2025).

Radiation hardness and post-irradiation annealing inform geometry and operational voltage selection for future upgrades.

6. Applications in High Granularity Calorimetry, Nuclear, and Astrophysics

P-type silicon detector arrays are currently deployed or foreseen in:

• High-energy physics calorimetry: Arrays form active layers in the electromagnetic and hadronic segments of calorimeters (HGCAL for CMS, FoCal for ALICE) (Sawan et al., 8 Aug 2025, Kałuzińska et al., 3 Mar 2025). Alternating silicon and absorber layers sample showers with high spatial granularity, aiding studies of photons, jets, and vector mesons in low-x QCD.
• Inverse kinematics nuclear experiments: Highly segmented annular arrays provide high energy and angular resolution for direct reaction studies, isotope separation via ΔE–E techniques, and precision cross-section measurements (Ota et al., 2023).
• Photon-counting and spectrometry: Delta-doped silicon arrays, typically with p-type accumulation layers, achieve near-unity internal quantum efficiency and >50% external QE in the far ultraviolet, supporting applications in space missions, biomedical imaging, and spectroscopic studies (Nikzad et al., 2016, Nikzad et al., 2011).
• X-ray beam diagnostics: Custom p-i-n ring arrays yield submicron sensitivity for in-situ beam profile monitoring in advanced light-source facilities (Yoon, 2018).
• Advanced imaging: Vertical nanopillar p-i-n arrays patterned on CNTs enable high-resolution, fast-response planar imaging for computed tomography and particle detection (Ahnood et al., 21 Jun 2024).

Arrays are routinely coupled to custom ASICs (e.g., HGCROC), phoswich detectors, and time-resolved readout electronics for optimized operation in these domains.

7. Future Prospects, Challenges, and Model Validation

Current and planned work addresses open technical and deployment challenges:

• Process enhancements: Routes for further improvement include triple guard ring implementation, process optimization to reduce defect-induced breakdown and leakage, and finer control of doping profiles.
• Full-scale prototypes: Fabrication of multi-layer Si–W calorimeter prototypes, with performance tests planned at CERN’s SPS and elsewhere, aims to validate operational energy resolution and uniformity in large experimental setups (Sawan et al., 8 Aug 2025).
• Simulation validation: Device simulation (TCAD, multi-grid Poisson solvers, Silvaco, Garfield++) is used to predict depletion, current response, and breakdown characteristics, with experimental data confirming reliability of numerical models (Kim et al., 2020).
• Mitigation of interface and bonding challenges: For advanced hybridization (e.g., covalent bonding to readout chips), interface engineering, passivation, and doping optimization are explored to overcome asymmetric depletion and charge loss (Wüthrich et al., 2022).
• Radiation damage modeling: DLTS, TAS, and TCT data inform the refinement of defect parameterization and bulk damage modeling for predictive simulation under HL-LHC fluence and operational annealing conditions (Villani et al., 26 Jun 2024, Kałuzińska et al., 3 Mar 2025).

A plausible implication is that ongoing progress in fabrication, characterization, simulation, and post-fabrication treatments will further expand the operational envelope and application space of p-type silicon detector arrays, supporting future experimental requirements at next-generation collider and rare isotope facilities.