Hierarchical Modeling & DSE Overview

• Hierarchical Modeling and DSE is a systematic approach that organizes complex design spaces using multi-level, recursively nested representations and directed acyclic graphs.
• It enables efficient exploration by rapidly pruning vast search spaces and co-optimizing architectural, microarchitectural, and mapping parameters.
• Surrogate models combined with Bayesian and heuristic optimization drastically improve energy efficiency, throughput, and design iteration speed.

Hierarchical modeling and Design Space Exploration (DSE) provide a systematic methodology for managing and optimizing the vast and complex parameter spaces characteristic of modern engineered systems—from AI accelerators to mixed-variable cyber-physical designs. Hierarchical modeling formalizes multi-level structure—often expressed as directed acyclic graphs or recursively nested formats—so that architectural and algorithmic choices can be efficiently evaluated, constrained, and co-optimized. DSE leverages these representations to rapidly prune, search, and optimize within a space that combines architectural topology, microarchitectural parameters, mapping/scheduling options, and even compositional reuse. The integration of hierarchy-aware surrogate modeling, IR-based simulation, and Bayesian or heuristic optimization underpins recent advances in scalable, accurate, and automated system design.

1. Foundations of Hierarchical Modeling in DSE

Hierarchical modeling expresses system structure using explicit, often recursively defined, compositional abstractions. In the context of hardware and system architecture, the hierarchy may span multiple levels—from fine-grained compute elements (e.g., ALUs, MACs), through subsystems (e.g., PEs, tiles, clusters), to board or system-of-systems integration. Hierarchical relationships are captured either through tree/DAG structures as in design space graphs (DSGs) (Saves et al., 27 Jun 2025), recursively composed intermediate representations (IRs) (Qu et al., 27 Mar 2025), or nested mapping tensors and loop nests (Mei et al., 2020).

A prominent scheme introduces "meta variables" that control the activation of "decreed" or "partially-decreed" subordinate variables, thereby supporting conditional, tree-structured parameter spaces. This modeling paradigm is generalized to mixed-variable domains (continuous, categorical, integer) and enables accurate encoding of inter-dependencies, exclusion constraints, and conditional bounds. Hierarchical kernels and appropriately defined distances further allow surrogate models to be constructed directly over these complex spaces (Saves et al., 27 Jun 2025).

In hardware design automation, HiVeGen exemplifies hierarchy by decomposing HDL code generation into multi-level modular instantiations, allowing iterative refinement and modular reuse (Tang et al., 2024).

2. Hierarchical Intermediate Representations and Mapping

Hierarchical hardware IRs formalize complex architectures using recursively defined compositions. MLDSE's hardware IR consists of two node types: SpacePoint (atomic storage or compute element) and SpaceMatrix (container of N-dimensional organization), parameterized by dimension, topology, and communication endpoints. Recursion allows arbitrary depth, e.g., tiles of cores within chiplets within clusters (Qu et al., 27 Mar 2025).

Workloads are captured as task graphs, with mapping IRs that specify assignment of tasks to SpacePoints (spatial) and their schedule/barrier relationship (temporal). Hierarchical mapping allows explicit modeling of synchronization (barriers) and cross-level communication primitives. This enables the integrated exploration of mapping strategies (e.g., tiling, sync, unrolling), and their interplay with diverse organizational choices.

In DNN accelerator DSE such as ZigZag, hardware-agnostic nested-for-loop representations are mapped to hardware hierarchies through binary mapping tensors $M_l$, which specify, for every operand type and loop dimension, the memory level(s) at which data are buffered and reused. ZigZag's novel support for uneven mappings (i.e., per-operand and per-tile mapping variability) vastly enlarges the mapping space, enabling superior exploitation of memory hierarchy (Mei et al., 2020).

3. Surrogate Modeling and Optimization over Hierarchical Domains

The complexity of hierarchical, heterogeneous design spaces necessitates advanced surrogate modeling techniques. Hierarchical GP surrogates are constructed by embedding each feasible configuration into an extended numerical space, assigning a special "excluded" value (EXC) for inactive variables. Per-variable distances are defined to robustly handle activity/inactivity, and composite SPD kernels are built via product kernels over neutral, meta, and subspace-activated variables (Saves et al., 27 Jun 2025). This approach allows surrogate models to respect conditional structure, and dimensionality-adaptive Bayesian optimization loops to efficiently propose promising configurations.

Search and acquisition are performed directly over the DSG-encoded domain. Pruning and imputation are supported: naïve random sampling is highly inefficient due to sparse validity, but hierarchical modeling improves sampling rate and discovery rate of valid/feasible candidates.

HiVeGen further integrates hierarchy-aware DSE directly into the code generation process. The search space is pruned at each level by leveraging coupling constraints, reducing exponential variable cross-product to manageable search sets ($S_{\rm flat} \to S_{\rm hier}$), and empirical evidence demonstrates 10–100× reduction in path enumeration (Tang et al., 2024).

4. Automated Simulation and Evaluation in Multi-Level Systems

A key advance in hierarchical DSE is the automated generation of simulators and cost models directly from the IR, enabling architecture, parameter, and mapping exploration without manual code adaptation. MLDSE achieves this through just-in-time code generation, producing event-driven simulators whose scheduling and resource contention logic is hardware-consistent, as derived from the hierarchical IR. The simulator is modular: each SpacePoint/SpaceMatrix defines its local modeling and contention semantics, and recursion handles arbitrary depth (Qu et al., 27 Mar 2025).

Temporal mapping IRs capture schedule hierarchies and cross-level synchronization, supporting accurate modeling of system-level phenomena such as compute–communication overlap and bank-level contention (Mo et al., 6 Apr 2026). DeepStack's dual-stage network abstraction and per-bank DRAM/buffer modeling yield cycle-accurate metrics at orders-of-magnitude faster simulation times than prior approaches.

In ZigZag, latency-enhanced analytical cost estimators combine mapping-tensor-derived access counts with parametrized energy and timing per memory level, enabling high-throughput Pareto evaluation (Mei et al., 2020).

5. Hierarchy-Aware Design Space Exploration Algorithms

DSE on hierarchical domains is structured as a multi-tier traversal over architecture space, parameterization, and mapping/scheduling strategies. Combined design spaces are expressed as products over architecture ($A$), hardware parameter ($H$), and mapping ($M$) choices (Qu et al., 27 Mar 2025). Optimization objectives include latency, energy, area, cost, and multi-objective criteria.

To address computational intractability, frameworks employ hierarchical search and pruning strategies: Pareto dominance, invalid configuration removal, infeasibility (e.g., memory overflow), and beam search over promising subspaces (Mo et al., 6 Apr 2026). In DeepStack, schedule search integrates parallelism axes (TP, DP, EP, SP, CP, PP, FSDP), tiling, collective algorithms, and hierarchical NoC/interconnect choices, encompassing $>$10$^{14}$ points. Empirical speedups arise from staged and constraint-aware enumeration, coupled with heuristic or iterative improvement (as in ZigZag’s mapping generator) (Mei et al., 2020).

Hierarchical code generation as in HiVeGen leverages module-level exploration and feedback: each candidate module is evaluated by PPA metrics, and the hierarchy prune-refines the subspace before invoking lower-level DSE (Tang et al., 2024).

6. Quantitative Results and Case Studies

Empirical evaluations consistently show substantial benefits of hierarchy-aware DSE:

• ZigZag achieves up to 33% greater energy efficiency compared to even-only mapping frameworks, with the uneven schedule search achieving near-optimality at substantially reduced runtime (Mei et al., 2020).
• DeepStack obtains up to 9.5× higher throughput versus ASTRA-sim baseline via coordinated architecture–parallelism DSE; end-to-end modeling error falls below 5% on real hardware (Mo et al., 6 Apr 2026).
• MLDSE demonstrates up to 1.4× performance advantage for many-core organization under equal area, and up to 30% latency reduction by optimal mid-level hierarchy in chiplet-based systems (Qu et al., 27 Mar 2025).
• HiVeGen achieves up to 45.24% runtime and 30.97% token savings for RTL generation, and identifies PPA-optimal designs in fewer iterations than canonical LLM-only baseline (Tang et al., 2024).
• In aircraft architecture, hierarchical surrogate and BO models reduce kernel hyperparameter count and outperform NSGA-II in fuel mass minimization, with faster and more reliable DoE sampling (Saves et al., 27 Jun 2025).

7. Broader Implications and Insights

Hierarchy is fundamental for scalability, parsimony, and interpretability in both modeling and optimization. Explicit encoding of hierarchical dependencies (via DSG, recursive IRs, mapping tensors) enables model parsimony, efficient sampling, and ultimately more tractable optimization. Surrogate-model-based Bayesian optimization over tree-structured spaces, hierarchy-aware code generation, and simulation-on-demand frameworks converge to a unified design paradigm for large-scale, heterogeneous systems.

A notable insight from DeepStack is that schedule–architecture codesign is essential: incomplete schedule search may lead to irrecoverably suboptimal silicon, unfixable by postfabrication tuning (Mo et al., 6 Apr 2026). This underscores the tight coupling between modeling, mapping, and system optimization.

Continued advances will likely integrate tighter cycle-level hardware models, automated DSE pruning, and increased integration with LLM-augmented design environments. The formalization of hierarchy in both modeling and exploration delivers critical leverage in the face of exponentially scaling design spaces in contemporary system design.