Scalable quantum error correction tailored for a heavy-hex qubit array

Abstract: To produce an operable quantum computer that is made with imperfect hardware, we must design and test scalable quantum error correcting codes that are suited for the devices we can build and, in unison, develop decoding strategies that accommodate device-specific noise characteristics. Here, we introduce the \emph{dynamic compass code}, a subsystem code with a novel syndrome extraction cycle, that has a competitive threshold while making efficient use of qubits arranged on a heavy-hex lattice. We use a superconducting qubit array to implement a distance-5 instance of this code, and demonstrate how detailed noise characterisation can boost decoder performance to yield significant improvements in logical error rates. We perform averaged circuit eigenvalue sampling (ACES) to acquire detailed context-dependent error information on all elements of the syndrome extraction process. Furthermore, we leverage soft information produced from measurement devices to augment the decoder with measurement error information and detect leakage errors for exclusion through post-selection. Our noise-informed approach yields up to 38.3\% improvement in the logical error rate of a distance-5 implementation of the dynamic compass code in experiment.

• The paper introduces the dynamic compass code (DCC) that exploits heavy-hex connectivity via weight-two and weight-four parity checks to achieve a fault-tolerance threshold.
• The approach integrates ACES-based noise characterization with soft decoding, yielding up to 38.3% reduction in logical error rates on specific measurement bases.
• Experiments on IBM's Heron-class processor validate the scalable design by demonstrating shallow syndrome circuits and device-aware improvements.

Scalable Quantum Error Correction Tailored for a Heavy-Hex Qubit Array

Introduction and Motivation

The paper "Scalable quantum error correction tailored for a heavy-hex qubit array" (2604.14296) addresses critical obstacles in quantum error correction (QEC) for superconducting devices with heavy-hex lattice topology. The authors introduce the dynamic compass code (DCC), a subsystem code constructed to exploit the heavy-hex connectivity, characterized by a dynamic syndrome extraction schedule combining weight-two and weight-four parity checks. Unlike the traditional heavy-hex code, which lacks a threshold required for scalable, fault-tolerant quantum computing, the DCC achieves a threshold—enabling arbitrarily small logical error rates for sufficiently large instances.

Dynamic Compass Code: Construction and Scheduling

The DCC overlays weight-four $X$-type and weight-two $Z$-type checks onto the heavy-hex lattice, where the measurement schedule is dynamically partitioned, reducing the complexity and stabiliser weight growth prevalent in heavy-hex and Bacon-Shor codes. The code is demonstrated experimentally as a distance-5 instance mapped onto IBM's Heron-class quantum processor, with the layout and checking schedule illustrated below.

Figure 1: Dynamic compass code schematic showing the heavy-hex qubit layout, check placement, and syndrome extraction schedule.

The measurement schedule maintains constant-weight detector checks as the code scales, allowing bounded error rates. This approach ensures the syndrome extraction circuits remain shallow and efficient, facilitating compatibility with mid-circuit measurements and controlling idle-induced decoherence.

Experimental Platform and Code Implementation

Experiments leverage IBM Quantum's 156-qubit Heron-class device, featuring high-fidelity two-qubit gates and mid-circuit measurement capabilities. The DCC is placed at two distinct locations (top-left qubits 46 and 65) and compared to conventional heavy-hex instantiations of equal code distance. The dynamic measurement schedule enables simultaneous measurement of subsets of $X$ and $Z$ stabilisers, minimizing circuit depth and error accumulation.

Noise-Informed Decoding Methodology

The decoder's efficacy depends crucially on accurate noise modeling. The authors adopt an exhaustive, device-specific noise characterization via Averaged Circuit Eigenvalue Sampling (ACES), producing gate-layer-resolved Pauli error models, including robust measurement error characterization. This ACES-based noise model is fed to high-performance matching decoders (BeliefMatching, PyMatching), both for hard decoding and augmented with soft information obtained from measurement IQ data.

Figure 2: IQ data characterization pipeline enabling extraction of state probabilities and leakage detection from raw measurement signals.

Soft decoding quantifies measurement outcome probabilities for $\ket{0}$, $\ket{1}$, or leakage ($\ket{2}$) states using Gaussian Mixture Models fit to IQ calibration data. This analog information is incorporated into the detector error model and exploited for leakage post-selection: rounds with elevated leakage probability are selectively excluded, reducing logical error contributions from rare leakage events. Detailed soft decoding variants target different classes of measurements (syndrome vs. data qubits) and attribute errors to distinct mechanisms (pre-, post-measurement, readout).

Strong Numerical Results and Comparative Analysis

The integration of ACES characterization in the decoder yields substantial reductions in logical error rates: 30.4% (X basis) and 9.4% (Z basis) relative improvements over conventional calibration-based decoding. Leakage post-selection using soft information further enhances performance, resulting in overall improvements up to 38.3% (X basis) and 24.2% (Z basis) in logical error rate per round for the distance-5 DCC. These improvements are robust across code placements and also manifest in heavy-hex code implementations, although the latter suffers from the lack of threshold in the X basis due to extensive stabilisers.

Figure 3: Memory experiment survival rates versus number of syndrome extraction rounds, illustrating logical error reductions across decoding strategies with ACES and soft IQ incorporation.

Figure 4: Memory experiment for the DCC on alternative placement; demonstrates spatial inhomogeneity impact on leakage abort rates.

Figure 5: Memory experiment for the heavy-hex code at default placement; baseline comparison against DCC.

Figure 6: Memory experiment for the heavy-hex code at alternative placement, showing susceptibility to device defects.

The per-round logical error rates are evaluated via linear fits of survival rates, and leakage probabilities are quantitatively analyzed across qubit placements, revealing spatial dependencies on leakage. The analysis includes a trade-off between logical error rate reduction and abort rates, confirming that modest post-selection (typically less than 4%) suffices to elide dominant leakage errors.

Figure 7: Comparison of soft-decoding variants for the DCC showing hard decoding versus soft decoding and leakage post-selection impacts on logical error.

Practical and Theoretical Implications

The DCC's threshold property and shallow syndrome circuits significantly advance the scalability of QEC tailored for heavy-hex lattice hardware. Full-cycle, device-specific noise modeling (ACES) and leveraging analog measurement information represent scalable methodologies applicable to processors with hundreds of qubits. The experimental gains are material for near-term demonstrations and forecast enhanced gate-level fidelity in future fault-tolerant architectures.

However, leakage post-selection is non-scalable for deep circuits due to increasing rejection fractions, motivating hardware-level leakage reset mechanisms as studied in recent work. Code performance is also limited by device inhomogeneity: defective qubits/couplers induce logical error bottlenecks and constrain code placement. Addressing fabrication defects through dropout-tolerant code architectures and adaptive scheduling will be essential as devices grow.

Conclusion

This work establishes the dynamic compass code as a scalable, hardware-aware QEC solution for heavy-hex arrays, validated experimentally on superconducting platforms. Device-informed decoding enabled by ACES and measurement soft information effectuate significant logical error rate reductions, with practical relevance for ongoing quantum processor development. The approaches demonstrated are extensible and set a clear direction for quantum error correction methodologies as qubit counts and operational fidelities improve.