Harmonic Backscatter Rectifier (HBR)

• HBR is an integrated RF circuit leveraging diode nonlinearity to enable simultaneous energy harvesting and backscatter communication via second and third harmonics.
• The design employs a shunt-diode rectifier and a DGS-based dual-band band-stop filter to ensure near-ideal f₀ matching and high rectification efficiency.
• Experimental evaluations show 50% conversion efficiency, 8 Mb/s uplink with <28 pJ/bit, and robust performance for batteryless, low-power tags.

A Harmonic-Backscatter-Rectifier (HBR) is an integrated radio-frequency (RF) circuit enabling simultaneous wireless power harvesting and backscatter communication by exploiting the nonlinearities of the rectification process to generate and modulate higher-order harmonics for uplink transmission. The key innovation of the HBR is the use of a single diode-based rectifier to simultaneously derive DC power and the second/third harmonic currents, which are then selectively reradiated using a dual-band, varactor-tunable band-stop filter implemented with a defected ground structure (DGS). This allows for low-power amplitude shift keying (ASK) modulation of both harmonics with preserved input impedance matching and rectification efficiency at the carrier frequency $f_0$, enabling high-throughput, low-energy uplink in batteryless or severely power-constrained tags (Che et al., 17 Jan 2026).

1. System Architecture and Functional Overview

The HBR comprises an antenna coupled through a matching network to a shunt-diode rectifier. Downlink RF energy at %%%%^^^^1^^^^%%%% is matched into the rectifier, where the diode nonlinearity produces a DC output (extracted after low-pass filtering) and synchronously generates second ($2f_0$) and third ($3f_0$) harmonic currents. These harmonics are not routed through a separate transmission chain; instead, a dual-band DGS-based band-stop filter, interposed between the rectifier and antenna, selectively modulates the amplitudes of the $2f_0$ and $3f_0$ components. Each harmonic can be independently modulated by biasing varactors that reconfigure the respective DGS resonators into or out of resonance, implementing parallel ASK on both channels. The DGS BSF ensures negligible impact on matching at $f_0$ (measured $|S_{21}| \approx -0.2$ dB, $|S_{11}| \approx −20$ dB), maintaining effective rectification and wireless power transfer.

2. Circuit Design and Implementation

2.1 Rectifier Topology and Matching Network

The rectifier employs a shunt-connected Schottky diode (SMS-7630), with a parallel capacitance ($C_2 = 0.05$ pF) for impedance tuning toward 50 Ω. A short-circuited microstrip stub of electrical length $\lambda_g/6$ at $f_0$ and characteristic impedance $Z_1$ provides a frequency-selective response: inductive at $f_0$ to cancel the diode junction capacitance, high impedance at $2f_0$ for harmonic suppression, and a short at $3f_0$ to maximize third-harmonic generation. The DC bias is extracted via 15 nH RF chokes and bypassed with capacitances ($C_1 = 22$ pF, $CL_1 = 22$ pF, $CL_2 = 6.8$ pF), with a 1 kΩ resistive DC load.

2.2 DGS-Based Dual-band Band-Stop Filter

The DGS BSF consists of two pairs of etched ground-plane resonators: a larger pair for $2f_0$ (3.4 GHz) and a smaller for $3f_0$ (5.55 GHz). Each is connected to a reverse-biased varactor (MA46H202-1056 for $2f_0$, MA46H071-1056 for $3f_0$). The applied bias (0–3 V) tunes the resonators’ effective resonance frequencies, moving their notches into or out of the signal band. Measured insertion loss confirms sharply defined notches: 18 dB at $2f_0$ and 23.7 dB at $3f_0$ for 3 V bias, while transparency at $f_0$ is preserved across bias states.

2.3 Frequency-Selective Impedance

The stub input impedance $Z_M(f)$ is given by:

$$Z_M(f) = \begin{cases} jZ_1 \tan\left( \frac{\pi}{6} f / f_0 \right), & f = f_0 \ -jZ_1, & f = 2f_0 \ 0, & f = 3f_0 \end{cases}$$

This configuration ensures optimized matching for rectification at $f_0$ and efficient harmonic generation.

3. Theoretical Characterization

3.1 Rectification Efficiency

The rectification efficiency is:

$$\eta_{rect} = \frac{P_{DC}}{P_{in}} = \frac{V_{DC}^2 / R_L}{P_{in}}$$

More generally, expressing the diode’s current as a Fourier expansion, $i(t) = I_s \left[ e^{v(t)/V_T} - 1 \right]$ with $v(t) = V_1 \cos\omega_0 t$, the $n$-th harmonic current $I_n$ is:

$$I_n = \frac{1}{T} \int_0^T i(t) e^{-jn\omega_0 t} dt$$

$\text{DC}$ power is $P_{DC} = V_{DC} I_{DC}$, and $P_{in} = \frac{1}{2} \text{Re}\{Z_{in}\} |V_1|^2$.

3.2 Harmonic Amplitudes

The reradiated voltage at $n\omega_0$ ($n = 2$ or $3$) is modeled as:

$$V_{n\omega_0} = Z_{ant} \frac{I_n}{Z_{ant} + Z_{DGS}(n\omega_0) + Z_{pn} + R_s + Z_M(n\omega_0)}$$

with $Z_{pn}$ the diode’s dynamic impedance at $n\omega_0$. $I_n$ approximates the $n$-th order Bessel term in the exponential expansion.

3.3 DGS Transfer Function

Each DGS resonator approximates a parallel RLC notch:

$$S_{21}(\omega) \simeq 1 - \frac{A_i}{1 + jQ_i\left( \frac{\omega}{\omega_{0i}} - \frac{\omega_{0i}}{\omega} \right)}$$

where $A_i$ is the notch depth, $\omega_{0i}$ and $Q_i$ the resonant frequency and quality factor of the $i$-th stop-band.

4. Modulation Mechanisms and Reconfigurability

ASK modulation on both $2f_0$ and $3f_0$ is realized by toggling the DGS BSF notches on/off via low-voltage varactor biases. With the DGS in resonance ($Z_{DGS} \gg 0$), harmonic reradiation is minimized (symbol "0"). With the DGS off-resonance ($Z_{DGS} \to 0$), low impedance enables maximal reradiation (symbol "1"). Two independent square-wave bias patterns with data rates up to 2 MHz per channel yield 4 Mb/s per harmonic, or 8 Mb/s total. The modulation is orthogonal and simultaneous on both $2f_0$ and $3f_0$.

5. Experimental Evaluation and Performance Metrics

5.1 Test Setup

The prototype HBR operates at $f_0 = 1.85$ GHz. Evaluation includes transmission through a cabled system, using a signal generator (−20 to 0 dBm), spectrum analyzer for zero-span ASK demodulation at harmonics, and varactor bias generation for modulation.

5.2 Measured Results

• DC Output and Efficiency: $V_{DC}$ increases from $\sim$0 V at −20 dBm to 0.78 V at 0 dBm input. Peak RF-to-DC power conversion efficiency (PCE) is $\approx$50% at –5 dBm. DGS modulation induces <1.23% absolute PCE drop at 0 dBm.
• Uplink Data Rate and Energy: At –10 dBm input, parallel 2 MHz ASK per harmonic yields 8 Mb/s aggregate uplink. Measured energy per bit for DGS switching: 20.9 pJ/bit ($2f_0$), 6.8 pJ/bit ($3f_0$); total $\approx$27.7 pJ/bit.
• RF-powered Tag Demonstration: Using an HBR, boost converter (BQ25504), RC oscillator, and SN74HC165 shift registers, −6 dBm input charges a 100 μF capacitor from 2.62 V to 3.28 V in 2.28 s (energy $\approx$194.7 pJ), supporting continuous dual-uplink at 12 kb/s with $<$64 nW system draw.

6. Design Advantages, Trade-Offs, and Implications

The HBR achieves simultaneous energy harvesting and harmonic backscatter uplink using a single nonlinear element and a compact, reconfigurable dual-band DGS BSF. This yields reduced component count and parasitics versus architectures with separate rectification and harmonic generation chains. Harmonic backscatter at $2f_0$ and $3f_0$ minimizes self-interference and multipath collision with the downlink at $f_0$, addressing a principal limitation of conventional RFID backscatter. Impact on f₀ matching and PCE is negligible ($<$1.3% drop), with the main trade-off being the area penalty for four ground-plane DGS resonators.

Empirical performance demonstrates 8 Mb/s uplink at –10 dBm input and $<$28 pJ/bit modulation overhead—a marked improvement over prior diode-impedance or varactor-bias tags (as tabulated in the cited work). This suggests the HBR topology is optimal for low-power, high-rate batteryless tags requiring both efficient energy harvesting and robust uplink, with extensions to higher-order harmonics or more advanced modulation schemes as plausible future directions (Che et al., 17 Jan 2026).