Hardware-Aware Multi-Objective Search

• Hardware-aware multi-objective search is a framework that balances predictive accuracy with hardware metrics like latency, memory, and energy through Pareto-optimal solutions.
• It leverages techniques from evolutionary algorithms, differentiable methods, and Bayesian optimization to efficiently explore complex design spaces.
• Practical applications include neural architecture search for mobile SoCs, FPGA, and quantum circuit design, achieving notable performance and resource savings.

Hardware-aware multi-objective search encompasses methodologies that seek models, circuits, or system configurations delivering optimal trade-offs between quality-of-service or predictive accuracy and various hardware efficiency metrics. Increasing deployment of deep learning and advanced algorithms on resource-constrained, heterogeneous hardware—such as mobile SoCs, FPGAs, ASICs, quantum devices, and cloud infrastructures—necessitates explicit multi-objective frameworks that account for device-specific latency, memory, energy, or cost, alongside primary functional objectives. Recent research formalizes the discovery of Pareto-optimal solutions in discrete, mixed-integer, or continuous design spaces, and develops algorithmic pipelines that efficiently generate diverse hardware-efficient architectures or circuits subject to real-world constraints.

1. Formal Problem Definition and Pareto Optimality

Hardware-aware multi-objective search is formulated as an optimization of vector-valued objectives over a discrete or continuous configuration space. For neural architecture search (NAS), quantum circuit design, or hardware/hyperparameter co-tuning, let $x \in \mathcal{X}$ denote a candidate solution (e.g., architecture, circuit, configuration). The problem is:

$$\min_{x \in \mathcal{X}}\, F(x) = (f_1(x),\, f_2(x),\, ...,\, f_m(x))$$

where $f_i$ are objectives (e.g., Top-1 error, inference latency on device $D$, model size, energy, training cost) specific to the hardware and application domain (Ito et al., 2023, Bouzidi et al., 20 Feb 2024, Benmeziane et al., 2021). Solutions are sought that are Pareto-optimal: $x^*$ is non-dominated if there is no $x$ such that $f_i(x) \leq f_i(x^*)$ for all $i$, and $f_j(x) < f_j(x^*)$ for some $j$. The set of such solutions maps onto the Pareto front in objective space.

Key problem specializations include:

• Hardware-aware NAS: $$(f_1(x),f_2(x)) = (\mathrm{Error}, \mathrm{Latency}_D)$$ or additionally FLOPs, model size, energy (Ito et al., 2023, Zhang et al., 2019, Sukthanker et al., 28 Feb 2024, Benmeziane et al., 2021).
• Hardware-quantization: objectives for error, speedup, energy, subject to memory and compatibility constraints (Rezk et al., 2021).
• Quantum circuit discovery: fidelity, depth, gate count, hardware implementability penalty (Potoček et al., 2018, Liu et al., 2 Dec 2025).
• Hardware/hyperparameter co-tuning: validation error, runtime, monetary cost (Salinas et al., 2021).

2. Algorithmic Strategies and Acceleration Techniques

A diverse algorithmic toolkit is applied to hardware-aware multi-objective search:

• Evolutionary Multi-Objective Optimization Algorithms (EMOA):
  • NSGA-II/SMS-EMOA: Maintain and evolve a population of candidate encodings, employing non-dominated sorting and diversity-maintaining (crowding/hypervolume) criteria (Ito et al., 2023, Bouzidi et al., 20 Feb 2024, Rezk et al., 2021).
  • Genetic Operators: Uniform/crowding sampling, crossover, mutation over vector representations, possibly guided by parameter importance scores or reinforcement learning (Bouzidi et al., 20 Feb 2024).
  • Hybrid Strategies: Ensembles, self-adaptive operator selection, and transfer learning to improve Pareto front coverage and convergence (Bouzidi et al., 20 Feb 2024, Salinas et al., 2021).
• Gradient-Based/Differentiable Approaches:
  • Supernet training: Decoupled training of over-parameterized supernets, with subsequent subnetwork extraction/post-search selection (Ito et al., 2023, Cummings et al., 2022).
  • Differentiable search: Scalarized or preference-conditioned loss functions, backpropagation through hardware proxies, hypernetwork-based joint encoding for multi-device adaptation (Sukthanker et al., 28 Feb 2024, Liu et al., 2 Dec 2025).
• Bayesian Optimization and Information-Theoretic Acquisition:
  • Surrogate-based search: Gaussian process or tree-based regressors model expensive objectives (hardware metrics), driving acquisition functions such as output-space entropy or expected hypervolume improvement (Belakaria et al., 2021, Belakaria et al., 2020, Zhao et al., 1 Jun 2024).
  • Uncertainty-aware and cost-sensitive selection: Explicit acquisition policies maximize information gain per hardware cost, and uncertainty-aware architectures are prioritized for evaluation (Belakaria et al., 2021, Belakaria et al., 2020).
• Partitioned/Hierarchical and Diversity-Driven Exploration:
  • LaMOO/meta-algorithms: Dynamically partition large search spaces, focusing exploration via classifiers (e.g., SVMs) and UCB-guided Monte-Carlo tree search in high-value regions, combined with baseline optimizers (Zhao et al., 1 Jun 2024).
  • Population diversity objectives: Additional diversity terms in the optimization (e.g., cost diversity) avoid premature convergence to narrow Pareto bands, enabling broader trade-off discovery (Sinha et al., 15 Apr 2024).

3. Modeling and Predicting Hardware Metrics

Given the non-differentiability and high expense of hardware measurements:

• Lookup Tables (LUT): Pre-profiled per-operator hardware metrics (latency, energy) indexed by architecture parameters (kernel size, width, etc.), demanding per-device calibration (Ito et al., 2023, Zhang et al., 2019).
• Learned Surrogates: MLPs, XGBoost trees, or radial basis function networks trained on a small set of measured examples, achieving high correlation with real hardware metrics (Spearman's $\rho$, Kendall's $\tau$ typically $>0.9$ with a few hundred samples) (Mao et al., 25 Sep 2025).
• Cost Modeling: Analytical FLOP/parameter formulas, direct device deployment, or memory-limited proxies. Some frameworks incorporate the surrogate prediction error or constant offset calibration as part of the evaluation pipeline (Ito et al., 2023, Benmeziane et al., 2021).
• Quantum Hardware Models: Incorporate device-specific noise parameters (gate errors, $T_1/T_2$, readout) directly in the objective evaluation for quantum circuits (Liu et al., 2 Dec 2025).

4. Constrained and Multi-Fidelity Search Protocols

Hardware-aware search often operates under constraints and varying fidelities:

• Constraint Handling: Explicit constraints (e.g., on memory, runtime, energy, cost) enforced via rejection, penalty functions, or directly within the multi-objective framework (Salinas et al., 2021, Benmeziane et al., 2021).
• Multi-Fidelity Evaluation: Surrogate models accommodate evaluations at varying simulator precision/epoch counts, allowing cost-aware exploration of the Pareto frontier with reduced high-fidelity calls. Output-space entropy and acquisition are adjusted for experiment cost (Belakaria et al., 2021).
• Early Stopping and A Posteriori Selection: Training and search stages are often decoupled, allowing rapid exploration and followed by targeted retraining or high-fidelity evaluation only for selected Pareto candidates (Ito et al., 2023, Benmeziane et al., 2021, Rezk et al., 2021).

5. Validation Benchmarks, Pareto Analysis, and Deployment

Hardware-aware search methods are evaluated on established datasets, device profiles, and benchmarks, with quantification of Pareto-optimality, convergence rate, and cost savings:

• Empirical Results:
  • OFA$^2$ recovers full trade-off curves (error vs. latency) in a single search for ImageNet-classification with measured device latency, outperforming random, single-constraint, or baseline approaches (Ito et al., 2023).
  • RAM-NAS demonstrates superior accuracy-latency trade-offs on robot edge hardware, with mutual distillation and candidate selection guided by real-device surrogate predictors (Mao et al., 25 Sep 2025).
  • LaMOO achieves 2–5× reduction in samples needed to reach global Pareto front compared to standard Bayesian optimization or evolutionary search (Zhao et al., 1 Jun 2024).
  • MOHAQ enables efficient quantization for edge deployment, balancing error, speedup, and energy on SiLago and Bitfusion devices through a two-stage beacon-based approach (Rezk et al., 2021).
  • QBSA-DQAS identifies noise-robust, expressive quantum circuits exploiting quantum-native attention and post-search compression for NISQ hardware (Liu et al., 2 Dec 2025).
• Metrics: Hypervolume, inverted generational distance (IGD), and dominance ratio are used to quantify front quality (Bouzidi et al., 20 Feb 2024). Empirical findings report up to $93.6\%$ Pareto dominance over vanilla NSGA-II and up to $2.42\times$ latency/energy reduction at no cost to accuracy.
• Deployment and Transferability: Hypernetwork, meta-agent and partitioned approaches enable zero-shot or sample-efficient transfer of Pareto-frontiers to previously unseen devices or resource targets (Sukthanker et al., 28 Feb 2024, Zhao et al., 1 Jun 2024).

6. Extensions, Open Challenges, and Future Directions

Current research underscores several open avenues:

• Device Heterogeneity: Optimizing for multiple, possibly dissimilar, hardware targets requires conditioning on device embeddings or simultaneous profiling (Sukthanker et al., 28 Feb 2024, Benmeziane et al., 2021).
• Integration of Compression, Quantization, and Pruning: Extending search spaces to support fine-grained compression (e.g., per-layer bitwidth) and compression–accuracy–energy Pareto fronts (Rezk et al., 2021, Benmeziane et al., 2021).
• Scalable Evaluation and Benchmarking: Standardizing latency, power, and memory metrics, and ensuring reproducibility across HW-NAS-Bench and similar platforms (Benmeziane et al., 2021).
• Algorithmic Innovations: Combining RL, EA, and BO, exploiting uncertainty—and information-theoretic selection, and adapting online to real-device measurements (Belakaria et al., 2021, Bouzidi et al., 20 Feb 2024, Fayyazi et al., 16 Jun 2025).
• Theoretical Guarantees: Formalization of transfer learning, surrogate calibration, and statistical validity in early pruning and candidate selection (e.g., conformal prediction methods) (Fayyazi et al., 16 Jun 2025).
• Quantum and Analog Design: Extending multi-objective search to novel computing paradigms including NISQ quantum devices and analog/RRAM hardware, accounting for noise, expressibility, and device-specific error (Liu et al., 2 Dec 2025, Potoček et al., 2018).

7. Practical Guidelines and Best Practices

• Predictor usage: Lightly trained surrogates suffice for early search guidance; periodic retraining/validation mitigates predictor drift (Cummings et al., 2022, Mao et al., 25 Sep 2025).
• Population diversity: Explicit diversity objectives (hardware-cost diversity, parameter randomization) should be used to prevent Pareto collapse and maintain long-term search robustness (Sinha et al., 15 Apr 2024).
• Replacement policies: Hybrid elitism, crowding metrics, and uncertainty ranking optimize convergence in evolutionary search (Bouzidi et al., 20 Feb 2024, Potoček et al., 2018).
• Pipeline decoupling: Separating supernet training from architecture selection or quantization allows a single optimization to yield diverse trade-off candidates adaptable to varied constraints (Ito et al., 2023, Cummings et al., 2022).

Together, hardware-aware multi-objective search methods provide rigorous frameworks for optimizing trade-offs in modern algorithmic design, bridging the gap between algorithmic innovation and practical, resource-constrained deployment on increasingly diverse hardware ecosystems.