H2RG-ASIC-MACIE System Architecture

• H2RG-ASIC-MACIE system is a detector-control architecture pairing a Teledyne HAWAII-2RG array, SIDECAR ASIC, and MACIE controller for efficient cryogenic-to-warm operation.
• It employs a custom buffered cable and a hybrid fast/slow readout mode to achieve up to 18 times faster full-frame acquisition compared to conventional slow modes.
• The layered hardware and firmware design enables precise control, calibration, and noise correction, ensuring performance consistency across near-IR and X-ray applications.

The H2RG-ASIC-MACIE system is a detector-control architecture built around a Teledyne HAWAII-2RG (H2RG) focal-plane array, a detector-proximate SIDECAR ASIC, and a room-temperature MACIE controller. In the cited literature, the clearest explicit implementation is the SCALES readout chain, written as $$\text{H2RG} \rightarrow \text{custom buffered flexible cable} \rightarrow \text{SIDECAR ASIC} \rightarrow \text{custom potted flexible cable} \rightarrow \text{MACIE card} \rightarrow \text{host computer/software}$$ (Benac et al., 28 Aug 2025). Closely related H2RG papers document the same basic cold–warm partition without MACIE—typically H2RG plus SIDECAR in the cryogenic domain, with a SAM board or custom FPGA controller outside the dewar—so the subject is best understood as one specific realization of a broader HxRG systems pattern rather than as the universal H2RG configuration (Sarkar et al., 2020).

1. Detector family and scope

The detector at the center of the system is the H2RG, but the literature treats more than one H2RG instantiation. In SCALES, each focal plane uses a Teledyne HAWAII-2RG HgCdTe detector with format 2048 × 2048 pixels, photosensitive area 2040 × 2040, 4 non-photosensitive pixels on each outer edge, 18 µm pixel pitch, and 4 outputs (Benac et al., 28 Aug 2025). In the NISP instrument electronics paper, the H2RG is likewise a near-infrared detector, described as a 2048 × 2048 HgCdTe/MCT array sensitive over 0.8 to 2.5 µm, specifically a 2.5 µm cutoff substrate removed MCT detector intended to operate at approximately 77 K in an LN$_2$-cooled environment (Sarkar et al., 2020).

A distinct branch of the literature concerns X-ray H2RG hybrid CMOS detectors. There, the cited H2RG is not a standard full-resolution near-infrared imager but a custom X-ray hybridized device. The detector identified as H2RG-122 has a 2048 × 2048 ROIC with 18 µm pitch, bump-bonded to a 1024 × 1024 absorber layer with 36 µm pitch, so that only one out of every four ROIC pixels is connected to a substrate pixel and the effective X-ray pixel size is 36 µm (Jr. et al., 20 Mar 2025). Earlier characterization of the same detector geometry emphasized that this sparse bonding was introduced to reduce interpixel capacitance crosstalk, yielding $1.8 \pm 1.0\%$ average adjacent-pixel IPC with no measurable asymmetry (Prieskorn et al., 2013).

This variety matters because the term “H2RG-ASIC-MACIE system” refers primarily to a readout architecture, not to a single detector material stack. The MACIE-based implementation in SCALES is a near-infrared HgCdTe system, whereas much of the high-detail H2RG ASIC literature is X-ray-specific and SIDECAR-based rather than MACIE-based. A plausible implication is that the system concept is portable across detector applications, while detector-intrinsic behaviors remain modality-specific.

2. Architectural partition and hardware chain

The defining structural feature of the system is the division between cryogenic detector-side electronics and warm controller-side electronics. In SCALES, the detector-side chain begins with the H2RG, continues through a custom buffered flexible cable and then a SIDECAR ASIC inside the detector head, and exits through a custom potted flexible cable to a room-temperature AstroBlank/Markury Scientific MACIE card (Benac et al., 28 Aug 2025). The custom detector–ASIC cable is not incidental: it includes extra resistors to allow buffered circuit readouts, and the paper states that this buffered readout is necessary for the hybrid operation.

The roles of the components are explicitly differentiated. The H2RG integrates the scene and presents analog outputs through its fixed 4-output architecture. The SIDECAR ASIC, located close to the detector, generates clocking patterns, manages detector readout, and digitizes data. The MACIE card is the room-temperature FPGA-based interface/controller supplying the communication and control layer between host computer and ASIC/detector; it is powered from 5 V and connected via gigabit Ethernet (Benac et al., 28 Aug 2025). The host computer then operates either through Markury’s GUI (MSAC) or through UCLA’s custom software using the MACIE API.

This cold–warm partition closely resembles the broader H2RG electronics pattern described in non-MACIE papers. NISP places the H2RG and the controlling SIDECAR ASIC inside an LN$_2$-filled cryogenic dewar, while the warm controller is outside the dewar at room temperature, implemented either as Teledyne’s SAM chain or as an in-house FPGA controller (Sarkar et al., 2020). In the X-ray H2RG literature, the same partition appears again: detector on a cold finger, Cryo-SIDECAR coupled by a cold strap, and additional support electronics such as a PSU Camera Interface Board for power, filtering, and data buffering (Chattopadhyay et al., 2018). The recurrent architectural lesson is that the H2RG system is never just the detector die; it is a detector-plus-ASIC-plus-warm-interface assembly.

Mechanical and thermal placement are part of the hardware definition. In SCALES, the SIDECAR ASIC sits inside each detector head close to the H2RG, G10 insulating structure provides thermal isolation between detector and ASIC regions, the ASIC is thermally strapped with copper, and detector heads were validated against thermal and electrical shorts after assembly (Benac et al., 28 Aug 2025). The IFS detector is additionally mounted on a linear focus stage driven by a cryoactuator.

3. Control stack, firmware, and host interfaces

The H2RG-ASIC-MACIE system depends on a layered control stack rather than on a monolithic controller. In SCALES, the MACIE hardware can be driven either through the vendor GUI MSAC or through a C/C++ API from Markury Scientific, while UCLA added a C-Python layer whose C library inherits from example code supplied by Markury (Benac et al., 28 Aug 2025). The Python layer is intended to follow heritage Keck control structure and interface to observatory systems via KTL (Keck Task Library).

The MACIE API functions described in the paper define the operational semantics of the warm controller. These functions include reading and writing SIDECAR ASIC registers, reading and writing MACIE registers, setting acquisition parameters, triggering acquisitions, and writing acquired data to FITS files (Benac et al., 28 Aug 2025). The system also relies on custom tuned firmware for the SIDECAR ASIC and customized firmware for the MACIE controller card to enable the hybrid fast/slow operating mode.

This host-side structure has strong continuity with earlier Teledyne HxRG control environments. In NISP, the Teledyne development chain is H2RG/ROIC to SIDECAR ASIC to warm development board to SAM board to a PC running Teledyne’s IDE and IDL/HxRG socket server software, with image data stored in FITS format (Sarkar et al., 2020). That paper also states that HxRG control software can configure multiplexer type (H1RG, H2RG, H4RG), the number of outputs (1, 4, 32), the detector readout mode, SIDECAR preamp gain, and acquisition modes such as up-the-ramp and Fowler. Although those statements are not MACIE-specific, they show the continuity of the host-side burden: register-level configuration, mode selection, acquisition scheduling, and FITS serialization remain essential regardless of whether the warm interface is SAM, a custom FPGA board, or MACIE.

One practical software issue exposed by the SCALES tests is the interaction between acquisition control and reference correction. The paper notes that reference pixel subtraction is implemented automatically in the MSAC GUI, whereas equivalent implementation in the Python interface was still in progress (Benac et al., 28 Aug 2025). This suggests that the observed image quality of an H2RG-ASIC-MACIE system is partly a property of the reduction pathway, not just of the analog front-end and controller hardware.

4. Readout modes, timing, and measured performance

The principal MACIE-specific contribution in the cited literature is the hybrid fast/slow readout mode developed for SCALES. The detectors came from the JWST/NIRSpec detector batch and were explicitly described as hard-wired to use 4 output channels, hard-wired to use the slow-mode analog preamplifiers, and intended for about 100 kHz pixel clock, which yields a minimum full-frame readout time of approximately 10.5 s (Benac et al., 28 Aug 2025). That operating point is too slow for a ground-based 2–5 µm instrument, because the infrared background saturates the detector before a full-frame read can complete.

The hybrid mode retains the detector’s slow-mode analog front-end but operates the SIDECAR’s ADCs in fast mode through the custom buffered cable and the MACIE control infrastructure. The paper reports tests and optimization of full-frame acquisition with pixel clock rates from 0.2–1.8 MHz; in the broader clock sweep, the imager was tested from 1.0–20 MHz master clock, corresponding to 0.2–4.0 MHz pixel clock and minimum frame times from approximately 5.25 s to 0.26 s, but performance degraded at master clocks $\ge 10$ MHz, so practical characterization focused on 1–9 MHz master clock, i.e. 0.2–1.8 MHz pixel clock (Benac et al., 28 Aug 2025).

The reported timing points define the demonstrated operating envelope:

• 1.0 MHz master / 0.2 MHz pixel: minimum frame time approximately 5.25 s
• 5.0 MHz master / 1.0 MHz pixel: minimum frame time 1.05 s
• 8.0 MHz master / 1.6 MHz pixel: minimum frame time 0.66 s
• 9.0 MHz master / 1.8 MHz pixel: minimum frame time 0.58 s
• 20 MHz master / 4.0 MHz pixel: approximately 0.26 s, but in the regime where degraded performance was observed

The paper’s headline timing result is therefore that hybrid operation enables readout up to 18 times faster than would be possible in slow mode alone, with the fastest demonstrated UCLA result being a minimum full-frame time of 0.58 s for the IFS detector (Benac et al., 28 Aug 2025). Acquisition modes tested include single reset-read, CDS, and Up-the-Ramp, with ramp lengths from 10 s to 1000 s.

The same paper also reports early detector characterization under MACIE control. For the imager, a photon transfer curve at a specific ASIC preamp gain setting yielded 5.74 e$^-$/DN, compared with the nominal 5.66 e$^-$/DN from the SIDECAR manual (Benac et al., 28 Aug 2025). CDS noise estimates show mode dependence: the imager measured 10.01 e$^-$ at 1.0 MHz pixel clock, improved to 4.919 e$^-$ at 1.5 MHz, 4.449 e$^-$ at 1.6 MHz, and rose again to 8.002 e$_2$0 at 1.8 MHz; the IFS remained comparatively stable at approximately 3.432–3.880 e$_2$1 across the same range, using the provisional electron conversion stated in the paper. The authors interpret these as preliminary results, not a complete final characterization.

A broader H2RG timing context appears in the X-ray SIDECAR literature, where the same detector family has been operated in 32-channel and 4-channel modes with frame times of 1.49 s and 10.65 s, respectively (Chattopadhyay et al., 2018). That comparison is not a MACIE result, but it shows that H2RG system performance is strongly conditioned by output multiplicity and controller mode.

5. Cryogenic operation, noise behavior, and calibration

Cryogenic support is a first-order subsystem rather than an accessory. In the SCALES MACIE implementation, the detector heads were installed in a test cryostat cooled by a closed-cycle refrigerator, with cryostat pressure about 10 µTorr, cryostat bench temperature about 80 K, detector operating temperature typically 35 K, and acceptable detector operating range observed at 35–39 K (Benac et al., 28 Aug 2025). Temperature control used Lakeshore 336 controllers; each detector head had two heater/sensor pairs, and the controlled temperature ramp rate was 0.5 K min$_2$2. During continuous operation, the ASIC-side exterior region of the detector head reached about 110 K, a result used to validate the thermal isolation design.

The importance of ASIC temperature is already well established in related non-MACIE H2RG systems. A Cryo-SIDECAR H2RG X-ray detector operated with detector temperature held at 130 K and SIDECAR temperature around 175–180 K achieved approximately 2.7% at 5.9 keV and read noise of approximately 6.5 e$_2$3, while the paper also reports that gain, resolution, and read noise showed no significant change in the 125–135 K region but began to degrade beyond roughly 150 K for the detector and 185 K for the SIDECAR (Chattopadhyay et al., 2018). This establishes that thermal management must cover both the detector and the controller ASIC; the detector alone is not the full performance driver.

Noise characterization in H2RG systems also extends beyond bulk read-noise metrics. The 2025 random-telegraph-noise study of H2RG-122 used archival data acquired with a cryo SIDECAR ASIC and SIDECAR Acquisition Module and identified RTN in 0.42 ± 0.01 % of pixels at 140 K and 0.060 ± 0.002 % at 160 K (Jr. et al., 20 Mar 2025). The detector was operated in up-the-ramp integration, analyzed using pseudo-CDS, and the paper emphasizes that RTN is tied to MOSFET behavior in source-follower pixel amplifiers. A plausible implication for MACIE deployments is that changing the warm controller does not remove detector-intrinsic pixel-amplifier noise mechanisms; RTN-aware calibration and bad-pixel screening remain relevant.

Calibration and reference correction are now an active part of the H2RG systems literature. “Simple Improved Reference Subtraction” is explicitly formulated for H4RG, H2RG, and H1RG detectors and uses embedded reference pixels with a least-squares Fourier-domain model that treats the left and right reference columns as two separate reference streams (Rauscher et al., 2 Feb 2026). The paper states that SIRS works with common HxRG clocking patterns, can often be applied in post-processing existing data if the reference pixels are present, and should be applied frame-by-frame before ramp fitting. Because the MACIE paper already highlights the role of reference pixel subtraction in the acquisition software, this H2RG reference-correction literature is directly relevant to the post-processing layer of an H2RG-ASIC-MACIE system even though MACIE itself is not discussed in that paper.

6. Position within the broader H2RG controller ecosystem

The phrase “H2RG-ASIC-MACIE system” can invite the misconception that MACIE is the standard or historically dominant warm interface for H2RG detectors. The literature here does not support that simplification. Only the SCALES paper explicitly documents a MACIE-based H2RG system (Benac et al., 28 Aug 2025). By contrast, the NISP electronics paper describes an H2RG-centered near-infrared instrument in which the H2RG and SIDECAR ASIC are mounted inside an LN$_2$4-filled cryogenic dewar and the warm layer is either Teledyne’s SAM board or an in-house Xilinx Spartan 6 FPGA controller on a Papilio Duo development board with separate clock generator and ADC & Bias daughter cards (Sarkar et al., 2020). That paper also details practical engineering points such as a 1.5-inch flex cable, separate analog and digital grounds tied at a common point, and a clean external 5.5 V supply to the SAM board.

The X-ray H2RG literature is even more explicit that system results must not be conflated with MACIE results. The major performance papers use SIDECAR ASIC / Cryo-SIDECAR, optionally followed by SAM or a PSU Camera Interface Board, not MACIE (Chattopadhyay et al., 2018). Their results are nonetheless indispensable because they define the controller responsibilities—clock generation, biasing, chip programming, amplification, ADC, and buffering—and show that cooling the ASIC materially changes H2RG system noise and spectral performance.

Detector-side studies add another caution. The specially configured X-ray H2RG-122 in earlier work was an engineering grade device with 16.31 e$_2$5 RMS read noise, $_2$6 IPC, and dark current of $_2$7 e$_2$8 s$_2$9 pixel$1.8 \pm 1.0\%$0 at 150 K (Prieskorn et al., 2013). Those are H2RG detector-system numbers obtained with SIDECAR™ + JADE-2 + JAC software, not with MACIE. They remain relevant because they show that detector architecture, hybridization pattern, and operating temperature can dominate image morphology and spectroscopic behavior independently of the choice of warm controller.

Within this ecosystem, the MACIE-based H2RG system is therefore best understood as a specific warm-control realization layered onto the established H2RG plus SIDECAR partition. Its distinctive features are the room-temperature MACIE controller, gigabit Ethernet host link, custom buffered detector–ASIC cable, and the hybrid fast/slow operating mode that made JWST-style slow-mode H2RGs viable for ground-based thermal-infrared use in SCALES (Benac et al., 28 Aug 2025). The broader literature shows that the underlying engineering questions—thermal management, multi-output synchronization, reference correction, detector-intrinsic noise, and host-side calibration—remain shared across MACIE and non-MACIE H2RG systems alike.