Grid-Forming Vector Current Control (GFVCC)

• GFVCC is a grid-connected converter control scheme that employs a vector current architecture to seamlessly transition from PLL-based grid-following to grid-forming control.
• It integrates positive- and negative-sequence controllers with modular components to regulate active/reactive power and ensure robust fault ride-through under both symmetrical and asymmetrical faults.
• GFVCC’s design supports multiple operational modes—including vector current fallback, virtual synchronous condenser only, and voltage downregulation—to balance current limiting with grid-forming performance.

Searching arXiv for recent and related papers on grid-forming vector current control and neighboring control paradigms. Tool unavailable in this environment. Proceeding with the arXiv papers provided in the prompt as the research basis, citing them directly. Grid-forming vector current control (GFVCC) is a grid-connected converter control scheme in which grid-forming behavior is realized through a vector-current architecture rather than through a purely voltage-source formulation. Recent research has shown that operating grid-connected converters using GFVCC offers significant benefits, including the simplicity and modularity of the control architecture, as well as enabling a seamless transition from PLL-based grid-following control to grid-forming. A central problem for the scheme is fault ride-through (FRT) under symmetrical and asymmetrical short-circuit faults, where the converter must provide fault current, stay synchronized to the grid, respect converter hardware limitations, and retain grid-forming behavior (Stanojev et al., 5 Aug 2025).

1. Definition and operating principle

GFVCC is organized around positive-sequence current-reference generation, optional negative-sequence current-reference generation, current limiting, and an inner current controller. Under balanced conditions, the positive-sequence controller regulates active and reactive power by controlling the $d$- and $q$-axis currents. In the rotating $dq$ frame, the paper states the standard approximations

$$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$

and derives the current references from a governor-like active-power droop and an AVR-like voltage regulator: $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$ The combined positive-sequence reference is then

$$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$

This control law is not presented as a conventional current-control overlay on a passive synchronization mechanism. Instead, the GFVCC structure combines a PLL, a virtual synchronous condenser branch, and a virtual current source branch. The resulting controller retains grid-forming behavior while remaining explicitly current-referenced. This suggests that GFVCC occupies an intermediate design space between classical PLL-centered vector current control and voltage-source-style grid-forming control, but the defining claim in the source is narrower: the architecture is modular and supports seamless transition from PLL-based grid-following to grid-forming (Stanojev et al., 5 Aug 2025).

2. Control architecture and sequence-domain formulation

The high-level GFVCC architecture is described in six parts: measurements and sequence extraction; positive-sequence grid-forming loops; negative-sequence control loops; current limiting; the inner current controller; and switching-stage and filter dynamics. Three-phase PCC and converter-terminal voltages and currents are sampled, and positive- and negative-sequence components are extracted by applying Park transforms at $\pm\omega$ followed by a notch or biquad filter centered at $2\omega$. The sequence-extraction filter is given as

$$G_\omega(s)=\frac{s^2+4\omega^2}{s^2+4\zeta\,\omega\,s+4\omega^2}.$$

For the positive sequence, the PLL estimates grid angle and frequency through a type-II loop,

$$\omega_r=\omega_n+\left(K_{\rm pll,p}+\frac{K_{\rm pll,i}}{s}\right)v_{q+}, \qquad \theta_r=\frac{1}{s}\omega_r,$$

while a virtual synchronous condenser is emulated by the virtual admittance

$q$0

with current

$q$1

The virtual current source branch supplies active- and reactive-current contributions from the governor and AVR loops, and the source states that superposition yields the total positive-sequence current reference: $q$2

The inner current controller is implemented as a stationary-frame proportional controller with feed-forward: $q$3 The switching stage and filter are modeled in $q$4 coordinates by

$q$5

$q$6

$q$7

The significance of this arrangement lies in its explicit modularity. The paper does not present GFVCC as a monolithic controller; rather, the sequence extraction, outer-loop objectives, current limiting, and inner-loop realization are separable elements. A practical tuning hint in the source is that the notch filters used for sequence extraction typically use damping $q$8 (Stanojev et al., 5 Aug 2025).

3. Negative-sequence extension and unbalanced current limiting

The paper extends GFVCC to asymmetrical faults by adding negative-sequence control loops in a modular manner. Three negative-sequence objectives are listed. The first is current balancing, implemented by setting

$q$9

The second is power-oscillation suppression. The third is voltage balancing, or negative-sequence mitigation, via a virtual admittance: $dq$0 An optional negative-sequence damping resistor is also included.

The positive- and negative-sequence references are combined into a $dq$1 reference vector, passed through a limiter, and then recombined into the three-phase current reference. The recombination step is expressed as

$dq$2

The negative-sequence signal paths each include a band-reject or notch filter to remove $dq$3 oscillations.

Current limiting is treated separately for balanced and unbalanced conditions. Under balanced conditions, if $dq$4, the reference is scaled to the limit: $dq$5 Under unbalanced conditions, two methods are described. The first is equal downscaling,

$dq$6

The second is negative-sequence priority, in which $dq$7 is first saturated at $dq$8 and the remaining headroom is then allocated to $dq$9.

A common oversimplification is to treat asymmetrical-fault operation as a purely positive-sequence overcurrent problem. The GFVCC formulation rejects that simplification by requiring explicit negative-sequence objectives and a priority-aware limiter when asymmetrical faults occur. In the source’s own recommendations, the negative-sequence objective should be chosen according to the relevant grid-code or power-quality requirement (Stanojev et al., 5 Aug 2025).

4. Fault ride-through modes under symmetrical and asymmetrical faults

For symmetrical faults, the paper defines three objectives: stay stable and avoid integrator windup, inject maximum current up to $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$0, and remain grid-forming and synchronized. It then introduces three modular fault modes selected by a fault flag.

Mode 1: Vector Current Control Fallback. The virtual synchronous condenser branch is disabled by setting $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$1, while the virtual current source remains active. The current references are immediately set to

$$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$2

corresponding to maximum reactive current injection. The PLL gains may optionally be widened to accelerate angle tracking. The paper characterizes the mode as simple, with inherent current limit and no windup, but also notes that it becomes grid-following during the fault, creating a risk of PLL “runaway” if the grid splits.

Mode 2: Virtual Synchronous Condenser Only. The PLL integrator is frozen or reset so that $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$3, and the AVR integrator is reset so that $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$4. The VCS currents are zeroed, and the total current is produced by the VSC branch alone: $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$5 A current limiter saturates the magnitude to $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$6, so the VSC acts as a current source of the required angle and magnitude. The stated advantages are retained grid-forming behavior, smooth recovery, and no integrator windup; the stated limitation is the need for PLL resynchronization after fault clearing.

Mode 3: Voltage Downregulation. The full GFVCC structure is retained and an integral loop is added on $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$7: $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$8 This reduces $$P \approx v_{d+} i_{d+}, \qquad Q \approx v_{d+} i_{q+},$$9 just enough to drive the current-reference magnitude to $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$0. The PLL and AVR continue to run normally. The paper characterizes the mode as fully grid-forming and smooth, without a mode switch, but requiring extra tuning and exhibiting slower response.

For asymmetrical faults, fault detection triggers the negative-sequence routines. The paper gives three example mappings between fault type and negative-sequence objective: a single-phase-to-ground fault may use power-oscillation suppression so that there is no DC-link ripple; a double-phase fault may use voltage balancing, absorbing negative reactive current to restore phase voltages; and a phase-to-phase-to-ground fault may set $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$1 if converter current balance is critical. The practical recommendations are explicit: for weak or islanded grids, Mode 2 is preferred to keep grid-forming intact; for strong grids, Mode 1 may suffice; and in Mode 2 the PLL and AVR integrators should be freeze-or-reset to avoid windup (Stanojev et al., 5 Aug 2025).

5. Case studies and reported performance

The paper analyzes the proposed FRT strategies through case studies including infinite-bus setups and multi-unit grids. In Case I, two parallel GFVCC inverters feed an infinite bus through filter and line impedance with $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$2 and $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$3. Each converter is rated at 100 kW, 400 V line-to-line, 50 Hz, with an LCL filter, PLL inertia emulation $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$4, damping $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$5, and current limit $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$6 pu. A three-phase short circuit is applied at $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$7 s and cleared at $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$8 s. The reported metrics are current injection reaching $$i_{d+}^{\rm ref}=\frac{P_{\rm set}+K_g(\omega_r-\omega_n)}{v_{d+}}, \qquad i_{q+}^{\rm ref}=K_V\int\bigl(\|v_{\rm pcc}\|-V_v\bigr)\,dt.$$9 pu, voltage dip of about $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$0, recovery time below $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$1 ms, and post-fault power injection resynchronizing to the setpoint. All three modes are tested, and Mode 2 is reported to show the best transient decoupling and the fastest voltage restoration.

In Case II, an IEEE 9-bus system includes two GFVCC units at buses 1 and 2 and one diesel generator at bus 3, with loads on buses 5, 7, and 9 of $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$2, $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$3, and $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$4 pu. A three-phase short circuit is applied at bus 5 from 0.5 s to 1.0 s. The converters inject up to $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$5 pu each, the diesel generator surges to about $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$6 pu, reactive excitation of the diesel generator is activated, and the converters share reactive power. The reported frequency nadir is about $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$7 Hz, with recovery within $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$8 s. The case description states that the voltage at the fault bus dips $$i_{dq+}^{\rm ref}=i_{d+}^{\rm ref}+j\,i_{q+}^{\rm ref}.$$9 and recovers to within $\pm\omega$0 in less than $\pm\omega$1 ms.

Metric	Case I Mode 2	Case II VSC only
$\pm\omega$2 [pu]	1.20	1.20
Voltage dip [\%]	15	40
Voltage recovery [ms]	180	240
Resynchronization time [ms]	200	300
Power oscillation (asym) [Hz]	0	0.1

The same source presents the above table as an “Example” comparison against grid-code requirements of at least $\pm\omega$3 rated fault current, at least $\pm\omega$4 allowed voltage dip, no more than $\pm\omega$5 ms voltage recovery time, no more than $\pm\omega$6 ms resynchronization time, and no more than $\pm\omega$7 Hz power oscillation under asymmetrical faults. One internal inconsistency should be noted objectively: the case description for Case II reports a $\pm\omega$8 fault-bus voltage dip, whereas the example table lists $\pm\omega$9 for “Case II VSC only.” The paper does not resolve that discrepancy in the extracted data (Stanojev et al., 5 Aug 2025).

6. Relation to adjacent hybrid voltage-current control research

GFVCC belongs to a broader research trend that combines voltage-forming and current-limiting characteristics in a single converter controller. A distinct but adjacent proposal is the hybrid voltage-current control of grid-forming and grid-following inverters, in which voltage control is introduced on the $2\omega$0-axis and current control is adopted on the $2\omega$1-axis, so that the inverter exhibits voltage-source characteristics on the $2\omega$2-axis and current-source characteristics on the $2\omega$3-axis. That work establishes a full-order model, analyzes port characteristics and small-signal stability, and validates the method on a 1.5 kW inverter experimental platform under varying short-circuit ratios (Wang et al., 4 Apr 2026).

The neighboring framework is useful for interpretation because it formalizes the voltage-source/current-source split through Thevenin-type $2\omega$4-axis behavior and Norton-type $2\omega$5-axis behavior. Its stated motivation is that conventional grid-following control may suffer from instability under weak-grid conditions, whereas conventional grid-forming control may exhibit unstable oscillations under strong-grid conditions. In the reported pole-locus analysis, PLL-based grid-following becomes unstable as SCR falls, while droop-based grid-forming becomes unstable as SCR rises; the hybrid controller remains stable over the tested ranges. This does not make the hybrid controller identical to GFVCC, since the underlying architectures and fault-mode formulations differ. A plausible implication, however, is that GFVCC can be read as part of a larger class of controllers seeking to preserve grid-forming attributes while embedding explicit current-source structure and current-limiting logic.

Within that larger context, the distinctive contribution of the GFVCC fault paper is not merely mixed-source behavior; it is the explicit construction of FRT modes for both symmetrical and asymmetrical faults, including negative-sequence control objectives, priority-based limiting, and modular transitions among fallback, VSC-only, and voltage-downregulation behavior. The paper’s concluding position is correspondingly practical rather than taxonomic: Mode 1 reverts to classic vector current control, Mode 2 uses only the virtual synchronous condenser and gives the best grid-forming performance, and Mode 3 downregulates back-EMF voltage without a mode switch but with additional tuning burden (Stanojev et al., 5 Aug 2025).