AC Fault Ride-Through in Inverter-Based Grids

• AC Fault Ride-Through is a control methodology that ensures inverter-based converters maintain synchronism and grid support during severe voltage disturbances.
• It employs a dual control approach combining emulated synchronous condenser and current-source loops with virtual impedance for handling balanced and unbalanced faults.
• Key performance metrics include current clamping at 1.1 p.u., fault ride-through for voltage dips as low as 0.15 p.u., and rapid recovery, ensuring grid code compliance.

An AC Fault Ride-Through (FRT) scheme is an advanced control methodology designed for power electronic converters—especially inverter-based resources (IBRs) in power systems with high renewable penetration—to maintain stable operation and grid support during severe AC faults such as voltage sags, phase jumps, and short circuits. Modern FRT schemes ensure compliance with evolving grid codes by integrating grid-forming behavior, explicit current limiting, virtual impedance shaping, and inertial response within converters. The state-of-the-art strategies, including those based on emulated synchronous condenser concepts, generalized per-phase droop, and coordinated voltage/current source actions, are critical for facilitating reliable transitions to inverter-dominated grids (Freytes et al., 2023, Bhagwat et al., 2023, Lin et al., 2 Feb 2024).

1. Conceptual Foundation of AC Fault Ride-Through

AC FRT targets three principal goals: (i) sustaining synchronous operation during voltage disturbances at the Point of Common Coupling (PCC), (ii) providing rapid support to grid voltage and frequency via active/reactive current injection, and (iii) enforcing converter thermal/electronic constraints during fault-induced current excursions. Unlike classic grid-following protocols that may trip on deep sags, grid-forming converters employing FRT schemes retain grid support throughout fault intervals—often for multiple cycles—by leveraging virtual inertia, synthetic swing equations, and current-limiting logics.

The ESC-based approach (Freytes et al., 2023) sets a reference framework: a voltage-source converter runs two parallel “virtual machines”—an emulated synchronous condenser implementing a virtual swing equation, and a current source that enforces power references and current limits. Grid voltages and currents are decomposed via a dual-synchronous reference frame, enabling positive/negative sequence control, virtual impedance compensation, and ellipse-based current saturation.

2. Control Architecture and Mathematical Formulation

State-of-the-art FRT controllers integrate sophisticated signal processing and multi-loop algorithms. The generic architecture involves:

• Measurement: Filter-side PCC voltages $\mathbf{v_s}$ and currents $\mathbf{i_s}$ are decomposed into symmetrical components (positive/negative sequence) using a Decoupled Double Synchronous Reference Frame (DDSRF).
• Emulated Synchronous Condenser (ESC) loop: Computes internal virtual power $P_{ESC} = v_{sdqpn} \cdot i_v$, feeds into a swing equation

$$\frac{d\omega_s}{dt} = \frac{1}{2H}\left( -P_{ESC} - K_D\,\omega_s\,(1 - LPF(s)) \right)$$

wherein $H$ is the virtual inertia constant, $K_D$ the damping coefficient, and $LPF(s)$ a fast washout.

• Current-source loop: Determines optimal injection via power droop ($P_{droop} = k_{droop}(\omega_s^* - \omega_s)$) and dynamically limits current using an ellipse-based saturation forcing

$\|i^+\|,\,\|i^-\| \le I_{lim}$

• Virtual-impedance compensation: For grid voltage regulation under balanced and unbalanced faults, the positive/negative-sequence current reference is solved as

$\begin{pmatrix}i_{vdp}\i_{vqp}\end{pmatrix} = \frac{1}{R_{vp}^2 + X_{vp}^2} \begin{pmatrix}R_{vp} & X_{vp}\-X_{vp} & R_{vp}\end{pmatrix} \begin{pmatrix}V^* - v_{sdp}\-v_{sqp}\end{pmatrix}$

with analogous equations for negative-sequence.

The practical implementation runs the entire control stack with fixed parameters; no fault-detection logic, switchable modes, or PLL freeze/unfreeze actions are required (Freytes et al., 2023).

3. Fault Ride-Through Mechanism: Dynamics and Workflow

The FRT mechanism is most critical during voltage sags, grid faults, and phase jumps. The sequence of operation is:

1. Fault Onset: Voltage sag detected at $\mathbf{v_{sdpqpn}}$—the virtual impedance block attenuates $i_v$ for voltage support.
2. Current Limiting: Combined reference $i_{ref} = i_v + i_{c.s}$ may breach thermal/current limits; elliptical limiter instantaneously clamps both positive/negative-sequence magnitudes at $I_{lim}$.
3. Swing Equation Integration: Despite current saturation, the ESC integrates on its internal virtual power $P_{ESC}$; the synthetic frequency and angle $\theta_s$ track grid dynamics, ensuring continuous synchronism.
4. Unbalanced Faults: Negative-sequence voltages trigger compensatory branches in the virtual impedance block; healthy sequence support is maintained, and the limiter enforces $I_{lim}$ equally across sequences.
5. Phase Jumps: Extreme jumps (e.g., –80°) are virtually absorbed by the ESC block, producing surges in instantaneous current up to $I_{lim}$ without violating device limits; post-disturbance, power droop ensures smooth setpoint recovery.

The ESC only “sees” internal virtual power, delegating all physical current to the current-source path, which remains governed by hardware limits.

4. Parameterization and Tuning Practices

Commensurate with grid codes, the FRT controller must be parameterized to balance ride-through capability, device protection, and system stability. For example (Freytes et al., 2023):

• Virtual inertia: $H = 2$ s (supports 100–200 ms faults)
• Damping: $K_D = 100$ s⁻¹ (enables overdamped recovery)
• Droop gain: $k_{droop} = 1/0.05$ p.u./Hz
• Virtual impedance: $L_v = 0.2$ p.u., $R_v = 0.05$ p.u., $\tau_v = 5$ ms
• Washout filter: $\tau_{LPF} = 1$ ms
• Current limit: $I_{lim} = 1.1$ p.u. (+10 % headroom)

These values are set to meet grid code FRT requirements (e.g., ride-through for voltage dips to 0.15 p.u. for at least 1 s; maximum current excursions limited to semiconductor thermal tolerances).

5. Performance Metrics and Grid Code Compliance

Benchmark simulations with a 2 MW BESS (as per (Freytes et al., 2023)) demonstrate:

• Fault ride-through time of 1 s for all fault types (single/two/three-phase faults on a weak grid: SCL=40 MVA).
• Voltage dips tolerated down to 0.2 p.u. (with extreme cases at 0.15 p.u.).
• All currents strictly clamped at $I_{lim}=1.1$ p.u.
• ESC-synthesized frequency $\omega_s$ remains stable; post-fault, frequency recovers to nominal (50 Hz) within 0.5 s.
• Under phase jumps, instantaneous virtual power surges up to ±2–4 p.u. without hardware overstress; frequency dip remains bounded (within 4–6 Hz) and follows droop recovery.
• No synchronism loss, tripping, freezing, or logic switching required.

The ESC+current-source architecture achieves unbroken operation under the most demanding grid events while strictly respecting device limits and code-mandated headroom.

6. Comparison to Conventional Schemes and Technical Advancements

Traditional FRT implementations rely on multi-mode logic (pre-fault, fault, post-fault), phase-locked-loop “freeze” strategies, fault detectors, and selective loop activation. These add complexity, risk loss of synchronism, or may breach ride-through requirements under unbalanced or severe faults. In contrast, the dual virtual-machine approach (Freytes et al., 2023):

• Implements grid-forming control with inertia/damping directly analogous to synchronous machines, even during saturation.
• Handles both balanced and unbalanced faults natively, including phase jumps and RoCoF, with no switchable logic.
• Removes need for PLL-based mode switching or freeze logic.
• Supports seamless verification against grid code via a single control structure.
• Provides superior simulation and real-system performance in terms of current clamping, frequency/voltage control, and recovery time.

This architecture constitutes a robust, unified solution for fault ride-through in high-renewable, converter-dominated grids.

7. Applications, Limitations, and Future Research Directions

The described ESC FRT scheme is validated on battery energy storage, but the underlying principles extend to utility-scale wind, PV, and mixed DER plants, including those with unbalanced feeder conditions (Bhagwat et al., 2023). Notably, generalized per-phase droop frameworks offer additional degrees of freedom for voltage-power unbalance management and flexible current limiting in unbalanced networks. Outstanding research areas include adaptation for hybrid AC/DC grids, optimization under network uncertainty, and integration with advanced protection/coordination strategies.

In summary, AC Fault Ride-Through schemes founded on parallel emulated synchronous condenser and current-source structures, equipped with sequence-aware virtual impedance and saturation logic, define the persistent technical frontier for converter-driven grid resilience under severe AC disturbance (Freytes et al., 2023).