Gatemon: Gate-Tunable Superconducting Qubits

• Gatemons are superconducting qubits that replace traditional SIS junctions with semiconductor weak links, enabling local electrostatic control.
• They combine the high coherence of transmons with dynamic gate-tunability, supporting fast single- and two-qubit operations via tailored Josephson energy.
• Advanced device architectures leverage engineered current-phase relations and scalable materials to mitigate decoherence and crosstalk in quantum processors.

A gatemon is a superconducting qubit architecture derived from the transmon but distinguished by its use of a proximitized semiconductor weak link (typically InAs/Al, Ge/Al, or related S–Sm–S systems) as the Josephson junction. This enables real-time, field-effect tunability of the Josephson energy via a gate electrode, replacing magnetic-flux-based tuning with local electrostatic control. Gatemons merge the high-coherence operational regime of the transmon with the mesoscopic and electric-field tunability inherent to semiconductor devices, providing a key pathway toward scalable, crosstalk-suppressed, and field-compatible superconducting quantum processors.

1. Fundamental Principles and Distinctive Physics

The functioning of gatemons is governed by replacing the SIS (superconductor–insulator–superconductor) tunnel junction of the conventional transmon with a highly transparent S–Sm–S weak link, such as a hybrid semiconductor–superconductor nanowire or a planar Josephson junction defined in a 2DEG or quantum well. The generic circuit Hamiltonian is

$H = 4 E_C (n-n_g)^2 - E_J(V_g) \cos \varphi,$

where $E_C = e^2/(2C_\Sigma)$ is the charging energy, $E_J(V_g)$ is the Josephson energy controlled via a gate voltage $V_g$ through the functional dependence of the weak link's transparency $\{T_i(V_g)\}$, and $\varphi$ the superconducting phase difference. Charge dispersion is exponentially suppressed in the transmon regime $E_J \gg E_C$.

A key distinction is the non-sinusoidal current-phase relation (CPR) of the S–Sm–S junction, with higher harmonics becoming significant as the junction transparency increases. This modifies the qubit anharmonicity and charge dispersion (Kringhøj et al., 2017, Liu et al., 15 Mar 2025). At high transparency, the qubit's nonlinearity is reduced relative to tunnel-junction transmons, with $\alpha \simeq -E_C(1-3\sum_i T_i^2/(4\sum_i T_i))$, approaching $-E_C/4$ in the ballistic limit.

2. Device Architectures and Material Platforms

Gatemons have been demonstrated in a range of device platforms:

• Nanowire-based junctions: Epitaxial InAs/Al or Ge/Al nanowires, with Al shell removed over a few 100 nm to define the weak link, and a side or top gate to tune the carrier density (Larsen et al., 2015, Huo et al., 2023, Zheng et al., 2023).
• 2DEG-based junctions: Planar Josephson weak links in InAs or Ge quantum well heterostructures with epitaxial Al, typically assembled into split-junction (SQUID) or single-junction configurations, often with top-gate voltage control (Casparis et al., 2017, Liu et al., 15 Mar 2025, Kiyooka et al., 2024, Sagi et al., 2024).
• Carbon nanotube and molecular junctions: Single-molecule (e.g., carbon nanotube) weak links with hBN encapsulation for reduced decoherence (Riechert et al., 3 Mar 2025).
• Planar SAG nanowires and CMOS-compatible stacks: Selective-area-grown InAs/Al nanowires and Ge/SiGe platforms, supporting monolithic, scalable arrays (Hertel et al., 2022, Sagi et al., 2024).

Capacitive shunt architectures (T-shaped, Xmon, floating or grounded islands) are engineered to control $E_C$, optimize charge stability, and minimize dielectric loss (Feldstein-Bofill et al., 2024). Variations include grounded and floating shunt capacitors, with grounded designs demonstrating superior frequency stability and coherence due to reduced charge sensitivity (Feldstein-Bofill et al., 2024).

3. Anharmonicity and Current-Phase Relation Engineering

Anharmonicity in standard S–Sm–S gatemons is typically reduced by a factor $E_C = e^2/(2C_\Sigma)$0 relative to SIS transmons, with measured values $E_C = e^2/(2C_\Sigma)$1 in the range $E_C = e^2/(2C_\Sigma)$2 to $E_C = e^2/(2C_\Sigma)$3 MHz for $E_C = e^2/(2C_\Sigma)$4–$E_C = e^2/(2C_\Sigma)$5 MHz (Kringhøj et al., 2017). This originates from the few-mode, high-transparency nature of the semiconductor junction. The effective Josephson potential, for channel transmissions $E_C = e^2/(2C_\Sigma)$6, is

$E_C = e^2/(2C_\Sigma)$7

giving rise to a unique spectroscopic signature that enables extraction of individual channel properties from the qubit spectrum.

A major advance is the realization of "gateless gatemon" devices in split-junction geometries, where destructive interference of first Josephson harmonics at half a flux quantum ($E_C = e^2/(2C_\Sigma)$8) leads to dominance of second and higher harmonics (Liu et al., 15 Mar 2025). This creates a strongly anharmonic double-well potential, observed to support $E_C = e^2/(2C_\Sigma)$9, i.e., $E_J(V_g)$0—orders of magnitude greater than in tunnel or ordinary single-junction semiconductor devices.

This enables Rabi frequencies exceeding 100 MHz (single-qubit gate times $E_J(V_g)$1 ns), well separated transitions for high-fidelity gate operation, and robust insensitivity to both first-order flux and charge noise (Liu et al., 15 Mar 2025). High-resolution qubit spectroscopy permits reconstruction of the full CPR, a capability inaccessible to standard DC transport.

4. Qubit Control, Coherence, and Readout

Single- and two-qubit gates in gatemon architectures utilize:

• X/Y control: Resonant microwave pulses applied to an XY drive line or the gate line. Typical gate times are 10–30 ns, with randomized benchmarking fidelities $E_J(V_g)$2 for single-qubit gates (Casparis et al., 2015, Hertel et al., 2022).
• Z control: Fast voltage pulses on the gate lines directly modify $E_J(V_g)$3 and hence the qubit frequency, enabling nanosecond-scale Z-rotations without resort to virtual gates (Casparis et al., 2015, Zheng et al., 2023).

Coherence times depend on materials and fabrication:

Platform	$E_J(V_g)$4 (μs)	$E_J(V_g)$5 (μs)	Remarks
InAs/Al nanowire gatemon	$E_J(V_g)$6–$E_J(V_g)$7	$E_J(V_g)$8–$E_J(V_g)$9	(Larsen et al., 2015, Huo et al., 2023)
SAG InAs/Al on Si	$V_g$0	$V_g$1–$V_g$2	$V_g$3 μs (Hertel et al., 2022)
Ge/SiGe planar or nanowire	$V_g$4–$V_g$5 (ns)	$V_g$6–$V_g$7 (ns)	Early devices (Kiyooka et al., 2024, Sagi et al., 2024)
2DEG InAs/Al	$V_g$8–$V_g$9	$\{T_i(V_g)\}$0	Dielectric loss dominated (Casparis et al., 2017)

Optimized circuits with grounded shunt designs have achieved $\{T_i(V_g)\}$1 up to 8 μs, $\{T_i(V_g)\}$2 up to 2 μs, and frequency stability (rms drift $\{T_i(V_g)\}$3 MHz over $\{T_i(V_g)\}$4–$\{T_i(V_g)\}$5 GHz) (Feldstein-Bofill et al., 2024). Maximum $\{T_i(V_g)\}$6 is currently limited by junction-intrinsic dissipation, not by Purcell, gate, or dielectric loss, with SIS references on the same chip consistently reaching $\{T_i(V_g)\}$7–$\{T_i(V_g)\}$8 μs (Sun et al., 31 Mar 2026).

Loss mechanisms unique to S–Sm–S devices include subgap states ("soft gap"), non-equilibrium quasiparticles, interface defects at the S–Sm boundary, and enhanced two-level-system participation within the nanowire weak link (Sun et al., 31 Mar 2026). Charge dispersion is strongly suppressed in the deep transmon regime but persists at lower $\{T_i(V_g)\}$9, especially in molecular devices where offset-charge noise is limiting (Riechert et al., 3 Mar 2025).

5. Multiqubit Coupling, Entangling Gates, and Control of Crosstalk

Gatemons support various two-qubit coupling schemes:

• Capacitive coupling: Direct capacitive coupling ($\varphi$0) between island pads gives a flip-flop Hamiltonian $\varphi$1 with swap rates $\varphi$2–$\varphi$3 MHz. Swap and iSWAP operations are realized by biasing qubits into resonance (Casparis et al., 2015, Casparis et al., 2017).
• Parametrically activated gates: Gate-voltage modulation of the tunable Josephson energy allows parametric excitation of CZ, iSWAP, $\varphi$4 at resonance frequencies $\varphi$5, yielding 75 ns gates with unitary error $\varphi$6 in the absence of decoherence (Chen et al., 2023).
• Controlled-Z gates: Using time-dependent coupling through an additional semiconductor coupler junction (tunable via a gate voltage), sub-50 ns, $\varphi$7 error CZ gates have been theoretically and numerically demonstrated for all-semiconductor and mixed transmon/gatemon architectures (Qi et al., 2018).
• Gateless- and split-junction schemes: In gateless split-junction geometries, higher Josephson harmonics can be exploited to further increase anharmonicity and reduce leakage during fast gating (Liu et al., 15 Mar 2025).

Gatemons benefit from field-effect tunability to dynamically suppress crosstalk, avoid frequency crowding, and switch couplings on/off electrically, bypassing the need for flux control and associated 1/f flux noise (Casparis et al., 2015, Pita-Vidal et al., 29 Dec 2025). Potential for operation in fields up to $\varphi$8–$\varphi$9 T supports integration with Majorana-based and spin qubits.

6. Limitations, Performance Challenges, and Device Optimization

Principal challenges for gatemon-based quantum processors, as established by recent benchmarking, include:

• Junction-intrinsic dissipation: State-of-the-art devices are limited by temperature-independent losses within the S–Sm–S weak link, potentially due to sub-gap states, imperfect interface, or local TLSs. Transmon references with identical circuitry but SIS junctions consistently yield $E_J \gg E_C$0 an order of magnitude higher (Sun et al., 31 Mar 2026).
• Frequency instability and hysteresis: S–Sm–S junctions exhibit greater gate hysteresis and frequency instability than SIS devices, attributed to mesoscopic disorder and charge traps. Grounded capacitor designs have been shown to suppress these effects to sub-MHz noise and drifts (Feldstein-Bofill et al., 2024).
• Reduced anharmonicity and leakage: At high channel transparency, anharmonicity is reduced, demanding fast pulses (< 10–30 ns) to minimize leakage out of the computational subspace. Split-junction and harmonic-engineered devices (e.g., gate-biased at flux sweet spots) overcome or exploit this by generating highly anharmonic potentials (Liu et al., 15 Mar 2025).
• Charge and quasiparticle noise: Despite suppressed charge dispersion in the transmon regime, offset-charge noise remains a decoherence source, especially in molecular (e.g., nanotube) or under-shunted junctions (Riechert et al., 3 Mar 2025).
• Dielectric and substrate loss: Losses from high-$E_J \gg E_C$1 substrates, normal-metal gates, and oxide dielectrics are significant in first-generation planar and nanowire devices, but are being rapidly addressed via new materials stacks (e.g., hBN, high-resistivity Si) and substrate removal (Hertel et al., 2022, Zheng et al., 2023, Sagi et al., 2024).

Empirically, state-of-the-art S–Sm–S devices exhibit $E_J \gg E_C$2–$E_J \gg E_C$3 μs (best $E_J \gg E_C$4 μs), $E_J \gg E_C$5–$E_J \gg E_C$6 μs, compared with $E_J \gg E_C$7–$E_J \gg E_C$8 μs in SIS reference transmons (Sun et al., 31 Mar 2026). Achieving $E_J \gg E_C$9 μs is essential to unlock $\alpha \simeq -E_C(1-3\sum_i T_i^2/(4\sum_i T_i))$0 two-qubit gate fidelities in parametric protocols (Chen et al., 2023).

7. Future Directions and Hybrid Architectures

Ongoing and future initiatives include:

• Material and interface engineering: Elimination of subgap states, enhancement of S–Sm interface hardness, and integration of quasiparticle traps are central to improving coherence (Sun et al., 31 Mar 2026).
• CPR and anharmonicity synthesis: Qubit designs leveraging engineered CPRs—using split-junctions, SQUID geometries, or atomic-scale-precision weak links—enable custom nonlinearities for protection, gate speed, and error mitigation (Liu et al., 15 Mar 2025).
• Field-compatible and hybrid nodes: Gatemons enable direct cQED coupling to topologically protected qubits (e.g., Majorana zero modes in hybrid nanowires (Huo et al., 2023, Pita-Vidal et al., 29 Dec 2025)), Andreev spin qubits, and parity-protected cos$\alpha \simeq -E_C(1-3\sum_i T_i^2/(4\sum_i T_i))$1 qubits in platforms like Ge/SiGe (Kiyooka et al., 2024).
• Scalability and integration: Selective-area-growth platforms allow monolithic, lithographically-directed arrays; gate-based control reduces wiring overhead, cross-talk, and favors integration with cryo-CMOS drivers (Hertel et al., 2022, Pita-Vidal et al., 29 Dec 2025).
• Ultrastrong coupling and parametric gates: Recent realizations of ultrastrong qubit-resonator coupling ($\alpha \simeq -E_C(1-3\sum_i T_i^2/(4\sum_i T_i))$2) open new regimes for ultrafast (sub-nanosecond) gate operations and non-JC circuit QED (Iglesias et al., 19 Mar 2026), as well as more flexible parametric gate activation (Chen et al., 2023).

Overall, the gatemon architecture provides a versatile, CMOS-compatible, and highly tunable platform for hybrid quantum processors, with device physics spanning the controllable landscape between macroscopic and mesoscopic Josephson circuits, and offering a critical interface between conventional superconducting and emergent topological qubits. Ongoing progress in materials, device engineering, and parametric operation is converging toward microsecond-scale coherence and high-fidelity operation essential for error-corrected, scalable quantum information processing.