Superconducting Transmon Qubit

• Superconducting transmon qubit is a weakly anharmonic oscillator that shunts a Josephson junction with a large capacitance to suppress noise and enhance coherence.
• The design leverages hybrid Sn–InAs nanowire junctions and side-gate modulation to achieve a tunable frequency range spanning 3 GHz with high-fidelity operations.
• Spectroscopic and coherence studies reveal relaxation times up to 27 µs and effective strategies to mitigate dielectric loss and Purcell decay for scalable quantum circuits.

The superconducting transmon qubit is a weakly anharmonic oscillator realized by shunting a nonlinear Josephson junction with a large capacitance. It is explicitly engineered to suppress charge noise sensitivity, resulting in a computational manifold robust for scalable gate operations. In recent years, the material palette has expanded beyond traditional Al/AlOₓ/Al junctions, enabling new regimes of tunability, coherence, and integration. Devices built with hybrid superconductor-semiconductor junctions, such as InAs nanowires with β–Sn superconducting shells, exhibit both strong electrical control and favorable energy scales, thereby advancing the prospects for high-fidelity quantum circuits.

1. Circuit Model, Hamiltonian, and Spectral Regime

The standard circuit realization comprises a single Josephson junction shunted by a large capacitance $C_\Sigma$, capturing the essential nonlinearity and energy storage of the system. The Hamiltonian in the charge–phase representation is

$$\hat H = 4 E_C (\hat n - n_g)^2 - E_J \cos\hat\varphi,$$

where

$$E_C = \frac{e^2}{2C_\Sigma},\quad E_J = \frac{\hbar I_C}{2e},$$

with $\hat n$ and $\hat\varphi$ conjugate number and phase operators, and $n_g$ an offset charge. In the transmon regime ($E_J/E_C \gg 1$), the first transition frequency is

$$\omega_{01} \approx \frac{1}{\hbar}\left(\sqrt{8E_CE_J} - E_C\right),$$

and the weak anharmonicity $\alpha \approx E_C$ provides addressability for two-level operation.

2. Sn/InAs Nanowire Junction Implementation

The hybrid implementation employs a wurtzite InAs nanowire (diameter 50–70 nm) grown on (001) InAs via VLS–MBE. A 15 nm β–Sn shell is deposited in situ at 85 K, covering half the wire circumference, and capped with 3 nm AlOₓ to suppress oxidation, although nonuniform capping may cause local dewetting. A semiconducting weak link of 70–120 nm is formed by shadow masking the shell, and the nanowire is ultimately placed across two NbTiN capacitor pads. Electrical contact is established by evaporated Al following Ar milling.

A nearby side gate modulates the carrier density in the junction, tuning $I_C$ between approximately 9 nA and 35 nA over $\Delta V_g \lesssim 0.5\ \mathrm{V}$, allowing $E_J(V_g)$ and, by extension, $\omega_{01}(V_g)$ to be rapidly modulated via gate voltage. This feature enables in-operando frequency control over a wide 3 GHz range.

Table: Frequency Tuning via Side Gate

$V_g$ (V)	$f_{01}$ (GHz)
0.95	3.5
1.10	4.5
1.25	5.7
1.38	6.6

At higher drive, the observed $|0\rangle\rightarrow|2\rangle$ two-photon features yield an anharmonicity $\alpha(V_g) \approx E_C/h \approx 200$ MHz, confirming stable addressable qubit operation.

3. Spectroscopic and Coherence Characterization

Comprehensive two-tone microwave spectroscopy reveals broad tunability of the qubit, with the frequency sweeps precisely tracking the carrier-induced modulation of $I_C$. Key relaxation and decoherence metrics are as follows:

• Maximum energy relaxation time $T_1^{\max} = 26.9 \pm 0.7\ \mu$s at $f_{01} = 3.494$ GHz.
• $T_1(f_{01})$ follows an inverse frequency trend, reflecting Purcell-limited decay and dielectric losses with effective $Q \sim 10^5$–$10^6$.
• Ramsey dephasing time $T_2^*$ ranges from $1.3$–$1.4\ \mu$s at high frequencies down to below $1\ \mu$s at low frequencies, marking enhanced charge dispersion as $E_J/E_C\rightarrow 10$.
• Echo dephasing time reaches $T_{2E} = 1.8 \pm 0.1\ \mu$s at the high-frequency optimal point ($f_{01}=6.616$ GHz), with $T_1(f_{01}) = 4.12\ \mu$s, ensuring $T_{2E} > 1/(2 T_1)$ as required for high-fidelity gates.

Extracted Decoherence Rates

Parameter	Value ($\mathrm{s}^{-1}$)
$1/T_1$	$3.7 \times 10^4$
$1/T_2^*$	$8 \times 10^5$
$1/T_{2E}$	$5.6 \times 10^5$

4. Decoherence and Noise Mechanisms

The dominant noise and decoherence sources in these devices are:

1. Dielectric loss associated with Si–NbTiN substrate and package, substantiated by resonator internal quality factor $Q_i$ increasing with photon number, indicating interacting two-level system (TLS) bath saturation.
2. Purcell decay through the readout resonator, with $Q_c\sim2000$ setting an upper bound on $T_1$ depending on mode detuning and coupling.
3. Charge noise—as $E_J/E_C$ lowers, the qubit's charge dispersion increases, leading to enhanced dephasing.
4. Spurious TLS whose coupling to the junction environment, although sporadic, can short-circuit isolation.

Ramsey data fit a combined exponential-Gaussian envelope, compatible with a classical $1/f$ charge noise model: $$S_n(\omega) = \frac{A}{|\omega|},\quad \langle\exp[i\delta\varphi(t)]\rangle \sim \exp\left[-\frac{1}{2}\left(\frac{\partial \omega_{01}}{\partial n_g}\right)^2 A t^2\right],$$ allowing extraction of charge noise amplitudes and quantification of dominant noise processes.

5. Materials, Fabrication, and Circuit-Level Optimization

Significant performance gains can be realized by improving both substrate and superconductor quality. Recommendations include:

• Transitioning to higher-quality substrates (sapphire, high-$\mu$ Si) and all-nitride ground planes (e.g., NbN).
• Enhancing Sn shell uniformity and resistance to oxidation via tailored in situ capping (e.g., atomic-layer AlOₓ).
• Employing less invasive wire-etching and “shadow-epi” nanowire contact formation to minimize residual contact resistance.
• Circuit design innovations: increasing shunt capacitance $C_\Sigma$ to decrease $E_C$ and push $E_J/E_C \gtrsim 50$, thereby further suppressing charge dispersion; embedding in Purcell-filtered networks to reduce resonator-driven decay; low-loss wiring and comprehensive magnetic shielding to abate flux and radiative losses.

6. Relevance, Outlook, and Comparative Context

Hybrid Sn–InAs nanowire transmons achieve coherence times $T_1\sim27\ \mu$s, $T_2\sim1.8\ \mu$s—metrics on par with early Al-InAs gatemon platforms and potentially extendable through identified materials and design optimizations. The larger superconducting gap of Sn ($\sim 600~\mu$eV vs $180~\mu$eV for Al) allows suppression of quasiparticle poisoning and opens the prospect of operation at elevated temperatures, facilitating integration with higher-power electronics and relaxed cryogenic requirements.

The rapid electrical tunability given by the InAs weak link supports agile qubit control, frequency allocation, and on-the-fly noise avoidance—key enablers for scale-out in multi-qubit architectures. This advances the state of the art in transmon technology, unlocking material degrees of freedom beyond the canonical Al/AlOₓ paradigm and opening pathways to scalable, high-coherence, and high-control superconducting qubits.