GAP9Shield: Histogram-less LiDAR SPAD Method
- GAP9Shield is a histogram-less direct Time-of-Flight approach for SPAD-based LiDAR sensors that uses linearized photon statistics to eliminate conventional histogram construction.
- The method employs both acquire-or-discard and time-gated schemes to mitigate SPAD dead-time and avoid pile-up, ensuring accurate depth extraction at high photon fluxes.
- Experimental validation demonstrates high depth precision with minimal per-pixel memory, outperforming traditional histogram-based systems in efficiency and scalability.
GAP9Shield refers to a “histogram-less” direct-Time-of-Flight (d-ToF) acquisition and estimation methodology for arrays of SPAD-based (single-photon avalanche diode) LiDAR sensors, specifically as implemented in 5×5 VL53L1-style ToF block arrays. This method eliminates the need for on-chip construction of timestamp histograms—historically required to overcome SPAD non-linearity—in favor of a scalable, resource-efficient approach based on linearized photon statistics and simple accumulations. The approach emulates dead-time-free SPAD behavior, enabling accurate ToF extraction at photon fluxes far beyond conventional pile-up limits while maintaining minimal per-pixel memory and robust depth precision under high ambient and background flux. This system architecture and methodology is detailed and mathematically analyzed in Tontini et al. ("Histogram-less LiDAR through SPAD response linearization" (Tontini et al., 2023)).
1. System Architecture and Acquisition Flow
The system repurposes each VL53L1 “block” (single pixel) to directly expose first-photon timestamps, eschewing conventional on-chip histogramming. Four on-chip registers per pixel are used: (background event count), (sum of background timestamps), (event count, laser on), and (sum, laser on). Acquisition consists of alternating laser OFF and ON phases, with both phases performed over an acquisition window , and repeated times per frame to ensure statistical robustness.
Within each phase, the incident Poisson photons are recorded such that systematic selection bias, typically due to SPAD dead-time (), is eliminated. Two hardware-level approaches achieve this:
- Acquire-or-Discard scheme: A simple comparator and register logic accept only one photon per enable window, discarding subsequent events until the next run, thereby ensuring each SPAD event is sampled after full reset.
- Time-Gated scheme: A programmable per-pixel enable delay line triggers SPAD activation, maintaining only the first arrival after each enable, with the absolute delay incremented post-detection, eliminating the possibility of event pile-up.
At the end of all runs, only the four per-pixel registers are needed for ToF computation, ensuring both memory and computational efficiency (Tontini et al., 2023).
2. SPAD Dead-Time Linearization Model
The theoretical analysis models the incident photon flux as (background) and (signal, laser-echo), with combined flux
For a dead-time-free SPAD, detected timestamps over are i.i.d., drawn from the normalized rate function . The mean timestamp is thus . Real SPAD dead-time introduces histogram distortion, biasing the earliest bins (pile-up). The described acquisition logic reforms the statistical process so every trigger samples a "fresh" detector, eliminating systematic undercounting and ensuring accurate photon statistics at high flux (Tontini et al., 2023).
3. ToF Extraction via Average-Timestamp Estimator
Once accumulation is complete, ToF is extracted using a closed-form average estimator: where is the intrinsic average laser-pulse time with respect to emission. Under uniform background, , enabling further storage reductions.
The variance of this estimator across frames is
with reflecting the spread in photon arrival times. This formula applies directly due to the linearization schemes, rendering dead-time effects negligible in the extraction, and ensures Cramer–Rao efficiency in the large-count limit (Tontini et al., 2023).
4. Multi-Pixel Array-Level Integration, Data Pipeline, and Calibration
The architecture assigns each VL53L1 pixel to route first-photon timestamps to a central controller (FPGA or ASIC). The controller manages the four registers per pixel, orchestrates the M-run acquisition phase, and computes per-pixel ToF values. Laser firing can be simultaneous for all 25 pixels, or temporally multiplexed depending on optical constraints.
Readout involves resetting counters, collecting statistics in alternating background/total (laser-off/on) modes, and streaming the 100-word register set () once per frame. Synchronization is achieved by distributing a global reference clock and a laser synchronization pulse to all blocks. Per-pixel time-skew and laser-pulse shape bias are calibrated by targeting a known planar reflector and recording measured ToFs. Residual calibration constants and are then updated to correct for systematic offsets.
Regular background-only acquisitions monitor and adjust for non-stationary background rates , ensuring consistent estimation fidelity across environmental conditions (Tontini et al., 2023).
5. Performance Metrics and Experimental Validation
Key performance metrics established by Tontini et al. for the GAP9Shield method include:
- Range up to 3.8 m (optical test setup constraint)
- Resilience to pile-up: linear operation up to 90% detection rate per bin, exceeding the classical 5% pile-up threshold by 18×
- Ambient tolerance to ~85 klux (142 Mph/s per chip)
- Per-pixel memory requirement: ~80 bits (2×16b counters, 1×32b accumulator), compared to ~8–10 kbits for a standard 1D histogram
- Accuracy: <0.5% of measured range with negligible background; <2% with moderate background; rising to ~10% at 75 klux
- Precision (1σ): <0.25% of range with no background; <6% at 15 klux; <21% at 75 klux (Tontini et al., 2023)
A mapping to commercial VL53L1 arrays (100 ps TDC resolution) predicts linear performance up to 1.5×10⁹ ph/s. With runs and typical , single-frame depth precision approaches 3 ps (∼0.5 mm at 3 m), though practical reflectivity and background elevate measurement variance to ∼1–2 cm at 3 m.
6. Implementation Recipe and Resource Comparison
Implementation involves (1) firmware modification to expose first-photon timestamps, (2) add-on of four small accumulators/counters per pixel, (3) global clock and laser synchronization distribution, and (4) choice of acquire-or-discard or time-gated logic per pixel. The FPGA-based controller manages run orchestration, register readout, ToF computation, and calibration. Systematic validation is performed against planar targets at controlled ranges and illumination. Parameter tuning of and allows tradeoffs between precision, frame rate, power, and laser duty-cycle.
The primary system-level advantage is the complete elimination of per-pixel histograms (∼kilobytes per pixel), replaced by compact registers (<100 bits per pixel), enabling support for high photon rates while maintaining depth precision and accuracy matching or exceeding conventional approaches (Tontini et al., 2023).