Automatic Floorplanning Engine

• Automatic floorplanning engines are integrated systems that automate the placement and partitioning of modules in VLSI, FPGA, and architectural designs.
• They employ advanced algorithmic frameworks, such as sequence pairs, graph-based encodings, and reinforcement learning, to optimize area, wirelength, timing, and power.
• These engines balance multiple objectives and constraints, leading to enhanced layout quality, reduced runtimes, and improved design feasibility.

An automatic floorplanning engine is an integrated computational system designed to automate the placement, partitioning, and optimization of spatial modules within a defined boundary under multiple physical and design constraints. In VLSI, analog/digital ICs, FPGA-based systems, and architectural and spatial planning, automatic floorplanning engines serve as core tools that transform high-level requirements into concrete module assignments, layouts, or space allocations while addressing critical metrics such as area, wirelength, power, routability, timing, and, where relevant, functional or adjacency constraints. The following sections provide detailed coverage of methodological advances, algorithmic frameworks, constraint management, multi-objective optimization strategies, benchmarked performance, and domain-specific applications.

1. Algorithmic Frameworks and Representations

Floorplanning engines employ a variety of algorithmic frameworks to represent and manipulate candidate layouts. Common representations include:

• Sequence Pairs, O-Tree, and B*-Tree: Encoded tree or sequence-based representations capture the ordering and adjacency of modules (or "blocks") for both slicing and non-slicing (arbitrary rectangular) floorplans. Pseudo-tree permutations and deterministic branching, as in GenFloor, allow exhaustive and systematic space exploration (Keshavarzi et al., 2021).
• Partitioned Sequence Triple (P-ST): The P-ST representation simultaneously encodes spatial, temporal, and scheduling relations. Hybrid nested sequence pairs (HNSP), a generalization of sequence pairs, capture both spatial groups (e.g., dynamically reconfigurable regions in FPGAs) and temporal groupings (time layers) (Chen et al., 2018). This enables the unified co-optimization of partitioning, scheduling, and floorplanning.
• Graph-Based Encodings: Several engines leverage layout graphs, netlists, or custom geometric graphs (e.g., Piano’s P2PRes graph (Xu et al., 20 Jul 2025), the use of layout graphs in Graph2Plan (Hu et al., 2020), and multi-layer graphs for pin assignment) to directly encode adjacency, connectivity, and geometric constraints.
• Density/Field or Physics-Inspired Models: In architectural domain engines, spatial assignment is driven by parametric or field-based models (e.g., the physics-inspired scalar “virtual field” allocation in (Li et al., 21 Jun 2024)), where spatial “mass” or influence fields determine cell allocation subject to thresholds for overlap and proximity.
• Markov Decision Process (MDP) Formulations: Engine state transitions correspond to sequential placement or assignment decisions, facilitating the application of reinforcement learning (RL), which is particularly impactful in analog floorplanning where explicit combinatorial search is infeasible (Basso et al., 20 Nov 2024, Basso et al., 27 May 2024, Basso et al., 17 Oct 2025).

2. Multi-Objective and Constraint-Driven Optimization

Automatic floorplanning engines universally operate as multi-objective optimizers, balancing diverse criteria depending on the domain:

• Area and Wirelength: Core objectives include area minimization (total cell/rectangle area or bounding box) and wirelength (typically measured as HPWL for inter-module connections).
• Timing/Performance: In IC and SoC design, engines such as MVLSAF incorporate timing-driven constraints, dualizing path delay constraints into convex cost flow formulations so that timing closure and slack distribution are not post-facto but integral to the solution (Yu et al., 2014).
• Power, Resource Utilization, and Level Shifting: Engines for multi-voltage SoCs (e.g., MVLSAF) integrate power-delay tradeoff (DP-curves), operating voltage selection, and level shifter overhead directly into the cost model using convex cost network flows and min-cost white space allocation (Yu et al., 2014).
• Routability and Pin Assignment: Routing-aware engines integrate routing congestion, precise pin locations, and resource reservation (e.g., dynamic routing resource estimation and pin capacity) both via geometrically-precise placement and via reward shaping in RL frameworks (Basso et al., 17 Oct 2025, Xu et al., 20 Jul 2025). Piano, for instance, uses a graph-based pin assignment method concurrently with module placement, resulting in direct improvements in routing ease and minimized feedthrough (Xu et al., 20 Jul 2025).
• Aspect Ratio and Boundary Constraints: Architectural and analog circuits often require that modules adhere to fixed outlines or aspect ratio ranges—incorporated via linear or quadratic penalty functions and enforced through post-processing or legalization phases (Li et al., 2022, Li et al., 21 Jun 2024).
• Hard Constraints and Legalization: Advanced engines (e.g., PARSAC (Mostafa et al., 9 May 2024)) integrate constraints-awareness natively within simulated annealing, supporting boundary, outline, and fixed pre-placement constraints not via soft penalties but through dedicated "constraint-fixing moves" and tailored tree representations (such as B*-tree with anchored blocks).

3. Core Computational Techniques

Floorplanning engines utilize advanced combinatorial, continuous, and machine learning optimization methods:

• Network Flow Algorithms: MVLSAF solves voltage and level shifter assignments as convex cost network flow and minimum cost flow problems, leveraging the convexity and decomposability of cost functions (Yu et al., 2014).
• Simulated Annealing and Metaheuristics: SA remains foundational (as in PARSAC), but modern engines enhance traditional move sets to address constraint sensitivity, or combine SA with ML-based initialization or RL-based policy search to accelerate convergence and legal solution discovery (Mostafa et al., 9 May 2024, Chen et al., 2018).
• ILP Post-Optimization: For FPGAs and heterogeneous platforms, engines often employ integer linear programming as a post-processor to ensure final legality, optimal margin within chip boundaries, and shape selection from precomputed candidates (Ding et al., 2022).
• Reinforcement Learning and Graph Neural Models: RL agents, sometimes augmented with relational GNN or R-GCN embeddings, sequentially select placements or assignments, with policy/value functions shaped to reward area compactness, routing success, and constraint adherence (Basso et al., 20 Nov 2024, Basso et al., 17 Oct 2025, Basso et al., 27 May 2024). Recent advances include beam search during inference for efficient trade-off navigation (Rovere et al., 8 May 2025) and large decision transformers adapted for 3D floorplanning (Amin et al., 15 Jun 2024).
• Evolutionary Strategies and Multi-Objective Genetic Algorithms: In architectural domains, non-dominated sorting (NSGA-II) and custom evolutionary operators enable the rapid exploration of competing Pareto-front solutions (e.g., maximizing usable area vs. minimizing overlap in (Li et al., 21 Jun 2024)).

4. Constraint Management and Legalization

Constraint management is fundamental across all domains:

• Timing and Functional Constraints: Constraint graphs (horizontal and vertical) in VLSI are used to enforce and legalize module overlap or relative placements after initial optimization (Li et al., 2022).
• Resource, Aspect Ratio, and Pin Constraints: Engines for modern FPGAs include detailed models for resource allocation schemes (e.g., balancing CLB, BRAM, DSP) (Goswami et al., 2020), aspect ratio at placement candidate filtering (Deak et al., 2019, Ding et al., 2022), and concurrent pin assignment to avoid routing bottlenecks (Xu et al., 20 Jul 2025).
• Routing-Friendly Placement: Routing-awareness is addressed through explicit integration of pin counts, pin locations, and resource padding. Pin-level information is embedded in graph neural models or used in convex padding/mask strategies to manage congestion and enforce design rule compliance (Basso et al., 17 Oct 2025).
• Hard Constraint Handling: CA-SA (PARSAC) demonstrates that constraint violations are best handled via dedicated moves that guarantee feasibility, rather than solely through cost penalties. Anchored blocks in modified B*-trees ensure exact pre-placement satisfaction (Mostafa et al., 9 May 2024).

5. Benchmark Results and Performance Evaluation

Performance evaluation in automatic floorplanning engines is multi-faceted:

• Wirelength and Area Improvements: MVLSAF demonstrated an average 8.5% power cost reduction with flexible multi-voltage assignment, and area and wirelength metrics comparable or superior to earlier methods—even with increased level shifter counts (Yu et al., 2014). Flat Poisson equation-based engines deliver 2–8% HPWL reductions in large benchmarks without hierarchical scaling overhead (Li et al., 2022).
• Runtime and Scalability: Recursive partitioning and candidate reduction (as in (Deak et al., 2019)) yield 90% runtime reduction relative to prior FPGA floorplanners; the beam search-augmented RL frameworks retain near state-of-the-art efficiency on CPU platforms (Rovere et al., 8 May 2025).
• Constraint Success Rate: Integrated optimization approaches (e.g., (Ding et al., 2022)) increase floorplan success and feasibility rates by 14% through ILP refinement, achieving rates close to 98% on heterogeneous FPGAs.
• Routing and Pin Assignment Metrics: Piano reduces mean HPWL by 6.81%, feedthrough wirelength by 13.39%, number of feedthrough modules by 16.36%, and unplaced pins by 21.21% compared to traditional post-floorplanning pin assignment flows (Xu et al., 20 Jul 2025).
• Analog IC Layout Quality: RL-based methods with R-GCN embeddings and routing resource prediction improve dead space, HPWL, and routing success simultaneously (e.g., 40.6% wirelength reduction, 73.4% routing success increase) (Basso et al., 17 Oct 2025), with layout completion times reduced by over two-thirds relative to manual placement (Basso et al., 20 Nov 2024).

6. Application Domains and Adaptability

Automatic floorplanning engines are applicable in:

• Digital VLSI and SoC Design: Engines supporting multi-voltage, timing-aware, pin-assignment-aware, and large-scale hierarchical designs (e.g., MVLSAF (Yu et al., 2014), Hier-RTLMP (Kahng et al., 2023), PARSAC (Mostafa et al., 9 May 2024)).
• FPGA-Based Systems: Approaches addressing partial reconfiguration, heterogeneity, dynamic region allocation, and adaptation to modern FPGA fabrics (e.g., (Goswami et al., 2020, Ding et al., 2022)).
• Analog and Mixed-Signal IC Layout: RL and GNN engines tailored to analog constraints, routability, device symmetry, and DRC compliance, integrating global routing and post-processing strategies (e.g., (Basso et al., 20 Nov 2024, Rovere et al., 8 May 2025, Basso et al., 17 Oct 2025)).
• Architectural Space Planning: Engines supporting adjacency-constrained, aspect-ratio-limited, and performance-driven space layouts in buildings and urban plans, leveraging parametric, physics-inspired, and evolutionary design frameworks (Li et al., 21 Jun 2024, Keshavarzi et al., 2021, Upasani et al., 2019).
• Interactive and Human-in-the-Loop Design: Generative and ML-based engines offering mechanisms for user-specified constraints and iterative design refinement (Graph2Plan (Hu et al., 2020), GenFloor (Keshavarzi et al., 2021)).

7. Advances, Limitations, and Research Directions

Automatic floorplanning engines have advanced significantly in constraint-integration, multi-metric optimization, routability sensitivity, and real-world utility. Open-source releases (e.g., PARSAC (Mostafa et al., 9 May 2024)) and tight integration with commercial flows (e.g., Xilinx Vivado integration in (Goswami et al., 2020)) have increased accessibility and industrial adoption.

Limitations highlighted in the literature include:

• Some engines have limited support for complex, higher-order functional or non-rectilinear spatial constraints (Hu et al., 2020).
• For certain RL and ML methods, integration of detailed router behavior and design-rule constraints remains imperfect, requiring iterative post-processing (Basso et al., 27 May 2024, Basso et al., 17 Oct 2025).
• Computational complexity may rise with extremely high-resolution grid representations or exhaustive combinatorial insertion/removal approaches, necessitating balance between solution diversity and runtime (Li et al., 21 Jun 2024, Chen et al., 2018).

Future work across domains is likely to explore:

• More expressive spatial models (non-Manhattan, curved, multi-level).
• Hybrid algorithmic pipelines combining ML, convex optimization, and metaheuristics.
• Closer coupling of floorplanning with detailed routing and physical realization.
• Improved user interface and constraint specification layers for interactive design.

Automatic floorplanning engines, in their current form, enable the co-optimization of functional, physical, and performance criteria in a manner that was historically impossible with manual approaches, underpinning advances in both microelectronic system design and architectural layout automation.