Fast Imaging Trigger (FITrig) Overview

• FITrig is an architectural design that integrates rapid trigger formation with imaging-informed selection across systems like MRPC TOF-PET, Cherenkov cameras, and radio telescopes.
• It leverages diverse hardware such as FPGAs, ASICs, and GPUs and employs methods like threshold discrimination, analog summing, and statistical analysis to reduce noise.
• By preselecting candidate events near the data path, FITrig minimizes processing loads while maintaining precise localization and timing performance.

Fast Imaging Trigger (FITrig) is a designation used in several technically distinct literatures for trigger systems that combine rapid event selection with imaging or localisation objectives. In the cited work, the term refers to a self-triggered acquisition chain for a Multi-gap Resistive Plate Chamber (MRPC) Time-of-Flight Positron Emission Tomography (TOF-PET) system, a trigger front end for imaging atmospheric Cherenkov telescope cameras, a FPGA-based telescope-level coincidence system with topological-trigger capability, and a GPU-accelerated, statistics-based method for ultra-long-period pulsar detection in radio images. Taken together, these uses suggest a family of architectures rather than a single standardized implementation: the common theme is that trigger formation is brought close to the data path, and only selected events or regions are passed to heavier read-out or localisation stages (Liu et al., 12 Feb 2025, Schwab et al., 2024, Zitzer, 2013, Li et al., 26 Sep 2025, Li et al., 6 Dec 2025).

1. Terminological scope and domain-specific meanings

In the available literature, FITrig spans detector electronics, telescope camera triggering, and radio-interferometric transient search. The implementations differ in signal model, hardware substrate, and decision statistic, but each is organized around fast rejection of uninformative or noisy data before downstream processing.

Domain	FITrig embodiment	Characteristic mechanism
MRPC TOF-PET	Self-triggered DAQ	Threshold discrimination, coincidence logic, continuous oscillation check
Imaging atmospheric Cherenkov telescopes	CT5TEA + CTC front end	Analog sums of adjacent channels, separate trigger and SCA sampling ASICs
VERITAS telescope-level trigger	FPGA camera trigger	Pixel neighbor coincidence, per-channel delay alignment, future image-moment logic
Radio interferometric pulsar search	Dual-branch FITrig	Tile-wise tLISI, z-scoring, optional FFT along time axis
FIP-TOI	TOI + FITrig pipeline	GPU-resident dirty snapshots, tLISI accumulation, thresholded trigger records

This distribution of usages indicates that FITrig is not tied to one detector class or one mathematical test. A plausible implication is that the term functions as an architectural label for systems in which fast trigger formation and imaging-informed selection are co-designed rather than separated into fully independent stages (Liu et al., 12 Feb 2025, Schwab et al., 2024, Zitzer, 2013, Li et al., 26 Sep 2025, Li et al., 6 Dec 2025).

2. Recurring architectural logic

Across the implementations, FITrig systems follow a similar control pattern. A front-end stage produces either conditioned analog signals or short-timescale images. A local decision stage then computes a primitive trigger quantity: a leading-edge threshold crossing in MRPC TOF-PET, a 4-pixel or 16-pixel analog sum in CT5TEA, a multiplicity condition over adjacent triggering pixels in VERITAS, or a tile-wise similarity-derived statistic in radio imaging. The result is then refined by coincidence logic, veto logic, temporal accumulation, or topological statistics before full read-out, source finding, or localisation proceeds (Liu et al., 12 Feb 2025, Schwab et al., 2024, Zitzer, 2013, Li et al., 26 Sep 2025).

The technical motivation is explicit in each domain. In the MRPC system, the objective is to suppress a high noise trigger rate while preserving precise gamma-ray detection. In Cherenkov cameras, the objectives are low trigger threshold, suppressed interference from the Switched-Capacitor Array (SCA), and narrow coincidence windows. In radio interferometry, the objective is to avoid running a conventional source finder on an entire image sequence and instead trigger it only on tiles with elevated statistics, or to bypass that step by operating in the image-frequency domain. This suggests a common FITrig design principle: expensive or high-volume downstream processing is activated only after a fast preselection stage has reduced the candidate space (Liu et al., 12 Feb 2025, Schwab et al., 2024, Li et al., 26 Sep 2025, Li et al., 6 Dec 2025).

3. FITrig in MRPC TOF-PET systems

In the MRPC TOF-PET implementation, the self-triggered front end and DAQ are described as five functional stages in series: MRPC detector to fast front-end amplifier; amplifier output to threshold discrimination; discriminator outputs to a coincidence logic unit; raw triggers to a continuous-oscillation check; and passed triggers to waveform read-out and storage. Each MRPC strip pair is read out differentially. The amplifier is a two-stage chain, LTC6430-20 to ADL5569, with $20\times20=400\,\mathrm{V/V}$ max gain, $>1.4\,\mathrm{GHz}$ bandwidth, and $<4\,\mathrm{ps}$ added jitter; the implementation details also state adjustable gain $20\text{–}100\times$, input range $5\text{–}50\,\mathrm{mV}$, and single-channel time jitter $<4\,\mathrm{ps}$. A leading-edge discriminator declares a hit when $A(t)$ exceeds a programmable threshold $V_{\rm th}$, nominally $100\,\mathrm{mV}$:

$$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$

A valid gamma-pair trigger requires hits from two opposing MRPC modules within a coincidence window $>1.4\,\mathrm{GHz}$0. The FPGA then applies a continuous oscillation check over a $>1.4\,\mathrm{GHz}$1 waveform segment following the first rising edge; if the number of additional rising-edge crossings $>1.4\,\mathrm{GHz}$2 exceeds a small integer, characterized as $>1.4\,\mathrm{GHz}$3, the event is vetoed. A baseline RMS filter also rejects events with $>1.4\,\mathrm{GHz}$4 above an approximately $>1.4\,\mathrm{GHz}$5 limit. Read-out is based on the DRS4 SCA chip, which continuously samples at $>1.4\,\mathrm{GHz}$6 into 1024 capacitors; after a valid trigger, stored charges are digitized by a 14-bit ADC at $>1.4\,\mathrm{GHz}$7 and transferred via PXI to a PC (Liu et al., 12 Feb 2025).

The reported performance figures are specific. The Noise Trigger Rate dropped from $>1.4\,\mathrm{GHz}$8 with threshold plus coincidence only to $>1.4\,\mathrm{GHz}$9 after the oscillation check. Time resolution was $<4\,\mathrm{ps}$0 FWHM for $<4\,\mathrm{ps}$1 gamma pairs. For localisation of a $<4\,\mathrm{ps}$2Na source, the TOF/COG method reconstructed $<4\,\mathrm{ps}$3 with $<4\,\mathrm{ps}$4, $<4\,\mathrm{ps}$5, and $<4\,\mathrm{ps}$6, whereas line-of-response intersection yielded $<4\,\mathrm{ps}$7 with $<4\,\mathrm{ps}$8, $<4\,\mathrm{ps}$9, and $20\text{–}100\times$0. The hardware summary states that these choices yield sub-200 ps system timing while rejecting $20\text{–}100\times$1 of noise triggers. The comparative discussion contrasts this FITrig implementation with conventional TOF-PET triggers using fast scintillator plus PMT or SiPM modules combined with single-channel CFDs or TDCs, external trigger scintillators, or simple threshold logic, which are described as having higher noise trigger rates in the Hz–kHz range, coarser time resolution of $20\text{–}100\times$2, and a rigid front end (Liu et al., 12 Feb 2025).

4. Cherenkov-telescope embodiments

For imaging atmospheric Cherenkov telescopes, FITrig appears in two related forms: the CT5TEA trigger ASIC used with its companion CTC digitizer ASIC, and the VERITAS upgraded telescope-level trigger system. In CT5TEA/CTC, the defining architectural decision is the physical separation of triggering and sampling. CT5TEA is a 16-channel, purely analog and discriminator trigger ASIC, while CTC performs SCA sampling and deep buffering. Each input channel is AC-coupled and DC-shifted by a per-channel 12-bit DAC, the 16 channels are grouped into four 4-pixel analog sums, a differential comparator generates a one-shot pulse if the sum exceeds threshold, and an external FPGA collects the LVDS outputs and forms camera-wide coincidences or read-out tokens. CT5TEA also provides a 16-sum node, Sum16, for camera-level or second-level sums. The measured trigger figures quoted in the detailed summary are $20\text{–}100\times$3, corresponding to approximately $20\text{–}100\times$4 photo electrons for a single-p.e. amplitude of $20\text{–}100\times$5, and $20\text{–}100\times$6, corresponding to approximately $20\text{–}100\times$7 p.e.; the abstract reports a minimal trigger threshold of $20\text{–}100\times$8 and trigger noise of $20\text{–}100\times$9. Comparator one-shot width is programmable from $5\text{–}50\,\mathrm{mV}$0 down to $5\text{–}50\,\mathrm{mV}$1, with run-to-run pulse-width jitter $5\text{–}50\,\mathrm{mV}$2 and inter-group skew $5\text{–}50\,\mathrm{mV}$3. The 4-sum trigger amplifier has small-signal 3 dB bandwidth of approximately $5\text{–}50\,\mathrm{mV}$4, the Sum16 node approximately $5\text{–}50\,\mathrm{mV}$5, and channel-to-channel coupling is $5\text{–}50\,\mathrm{mV}$6 up to $5\text{–}50\,\mathrm{mV}$7, falling below $5\text{–}50\,\mathrm{mV}$8 for 10 ns pulses. The integration summary states that a global FIFO in the FPGA tags each hit with a $5\text{–}50\,\mathrm{mV}$9 phase-locked timestamp shared with CTC (Schwab et al., 2024).

The VERITAS trigger upgrade exemplifies a telescope-level FITrig built around FPGA neighbor coincidence. Each telescope contains an L2 crate with 10 input boards, 3 L1.5 boards based on Xilinx Virtex-5 FPGAs, and an L2 board based on a Xilinx Virtex-4 FPGA. The camera is partitioned into three overlapping regions. A level-2 hit is generated when the multiplicity criterion $<4\,\mathrm{ps}$0 is satisfied for a center pixel and its adjacent neighbors within a programmable coincidence window $<4\,\mathrm{ps}$1, with an extra programmable overlap requirement $<4\,\mathrm{ps}$2 allowing the effective coincidence window to be reduced from routing-defined $<4\,\mathrm{ps}$3 to as small as $<4\,\mathrm{ps}$4. Time alignment is obtained by measuring raw arrival times with a calibration LED flasher and downloading per-channel delays in $<4\,\mathrm{ps}$5 steps over a $<4\,\mathrm{ps}$6 range. The post-alignment spread was $<4\,\mathrm{ps}$7, and the system could operate with an effective coincidence window of approximately $<4\,\mathrm{ps}$8 while maintaining $<4\,\mathrm{ps}$9 uniform efficiency. The accidental night-sky-background rate for the 3-fold logic scales approximately as $A(t)$0; narrowing the gate from 8 ns to 5 ns reduces the accidental rate by roughly $A(t)$1, corresponding to a reduction greater than $A(t)$2. The commissioning summary reports $A(t)$3 uniform camera response relative to the pre-upgrade system, operational coincidence windows programmable from $A(t)$4 with an optimal setting near $A(t)$5, and a hardware threshold reduction from approximately $A(t)$6 to approximately $A(t)$7. The same FPGA also computes bit-pattern image moments, including $A(t)$8, $A(t)$9, $V_{\rm th}$0, $V_{\rm th}$1, $V_{\rm th}$2, and $V_{\rm th}$3, to support a future topological trigger, although that capability is described as not yet deployed (Zitzer, 2013).

5. Statistical and GPU-resident FITrig in radio astronomy

In radio astronomy, FITrig is formulated as a statistics-based trigger for ultra-long-period pulsars in wide-field interferometric images. The 2025 formulation introduces two complementary branches. In the image-domain branch, FITrig computes a tile-wise similarity index, tLISI, between successive difference images, converts it to a complementary difference score $V_{\rm th}$4, computes the z-score $V_{\rm th}$5, and triggers a conventional source finder such as SOFIA 2 only on tiles with $V_{\rm th}$6 above a threshold $V_{\rm th}$7, for example $V_{\rm th}$8. In the image-frequency-domain branch, FITrig stacks the time series of tLISI values for each tile into a three-dimensional cube, performs an FFT along the time axis, applies harmonic summing or selects the maximum spectral magnitude $V_{\rm th}$9, computes $100\,\mathrm{mV}$0, and thresholds selected tiles before position refinement. The statistical model assumes that under $100\,\mathrm{mV}$1 each pixel intensity is Gaussian, $100\,\mathrm{mV}$2, and that adjacent-snapshot noise in the difference images remains approximately Gaussian with zero mean and variance $100\,\mathrm{mV}$3. The tile statistic is defined as

$100\,\mathrm{mV}$4

where $100\,\mathrm{mV}$5, $100\,\mathrm{mV}$6, and $100\,\mathrm{mV}$7 are the mean, maximum, and weighted mean terms defined over a tile, and by the Central Limit Theorem $100\,\mathrm{mV}$8 for large tile size. A candidate is declared when $100\,\mathrm{mV}$9, with one-sided false-positive probability $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$0 (Li et al., 26 Sep 2025).

The implementation is explicitly GPU-oriented. Tiles are independent, each CUDA thread block handles one tile, shared-memory reductions compute partial sums and maxima, and the image-domain pipeline transfers three consecutive snapshots to the GPU, launches the tLISI kernel, downloads the $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$1 matrix, computes $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$2 and $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$3 on the CPU, thresholds, and forwards only selected tiles to SOFIA 2. The reported complexity is $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$4 for the tLISI kernel, $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$5 for the frequency branch FFT, and $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$6 for SOFIA 2 on a full image, with FITrig reducing the latter to $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$7 where $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$8. On an NVIDIA H100 with $$\mathrm{Hit}_i(t)= \begin{cases} 1, & A_i(t)\ge V_{\rm th}\ 0, & A_i(t)<V_{\rm th} \end{cases}$$9 images, image-domain FITrig plus SOFIA 2 on selected tiles is reported as $>1.4\,\mathrm{GHz}$00 faster than SOFIA 2 alone. At a $>1.4\,\mathrm{GHz}$01 threshold on $>1.4\,\mathrm{GHz}$02 MeerKAT-simulated noise images, SOFIA 2 alone yields approximately 3840 false positives, whereas FITrig reduces this to approximately 5–90 candidates, corresponding to suppression by up to $>1.4\,\mathrm{GHz}$03; the image-frequency branch leaves only 1–5 candidates across a wide range of pulsar faintness and sampling rates. FITrig is reported to detect pulsars with flux down to $>1.4\,\mathrm{GHz}$04 of surrounding steady sources, to remain robust even at $>1.4\,\mathrm{GHz}$05 with $>1.4\,\mathrm{GHz}$06, and in MeerKAT observations of PSR J0901-4046 to recover a period at $>1.4\,\mathrm{GHz}$07 with FITrig spectrum SNR approximately 70.3 and full end-to-end detection in 6.34 s for 1500 snapshots on H100, with arcsec-level localisation after spline interpolation (Li et al., 26 Sep 2025).

A later integration, FIP-TOI, embeds FITrig in a GPU-resident imaging pipeline. The Transient-Oriented Imager (TOI) reads UVW and DATA from a CASA MeasurementSet, performs SVD/PCA on the $>1.4\,\mathrm{GHz}$08 baseline matrix, projects onto a 2-D grid, applies gridding weights, performs a single 2-D inverse FFT, and produces a dirty snapshot on the GPU. FITrig consumes a sliding window of three consecutive dirty snapshots, divides each snapshot into small tiles such as $>1.4\,\mathrm{GHz}$09 pixels, computes tile-wise tLISI, accumulates tLISI over time into a 3-D cube, reduces in time by summation, computes per-tile z-scores, applies a detection threshold, and emits tile coordinates with timestamps. The tLISI is defined directly as a complement of tile-level change terms, so lower tLISI indicates a stronger change, and the z-score is written as

$>1.4\,\mathrm{GHz}$10

All dirty snapshots remain in GPU global memory; only the final tLISI or z-score matrices are copied to host. Reported timings on an NVIDIA H100 for one $>1.4\,\mathrm{GHz}$11 image are approximately 4.5 ms for TOI, approximately 6 ms for the FITrig tLISI kernel plus z-score stage, and approximately 10 ms total GPU time per snapshot, excluding once-only planning. Compared with a WSClean-based pipeline, the reported speed-up is $>1.4\,\mathrm{GHz}$12 on SKA1-LOW, $>1.4\,\mathrm{GHz}$13 on AA2, and $>1.4\,\mathrm{GHz}$14 on MeerKAT for $>1.4\,\mathrm{GHz}$15 images. Additional reported figures include augLISI$>1.4\,\mathrm{GHz}$16, TOI noise approximately 30–40% lower, worst-case corner clipping of approximately 8.6%, maximum tLISI difference below $>1.4\,\mathrm{GHz}$17 per tile on GLEAM data, and true-tile z-scores of 68.8 in simulation and 54.6 in real PSR J0901-4046 data, with no missed detections (Li et al., 6 Dec 2025).

6. Comparative interpretation, misconceptions, and limitations

The cited literature does not support treating FITrig as a single algorithm, ASIC, or trigger protocol. Instead, it is applied to domain-specific systems with different observables: voltage crossings and waveform morphology in MRPC TOF-PET, analog sums and pixel multiplicities in Cherenkov cameras, and tile-wise image statistics in radio interferometry. This suggests that FITrig is better understood as a design pattern centered on rapid, imaging-aware preselection. The factual differences are substantial. In MRPC TOF-PET, FITrig is a self-triggered DAQ chain with threshold discrimination, coincidence logic, oscillation veto, and DRS4 waveform capture. In CT5TEA/CTC, it is an analog-sum trigger front end whose separation from the SCA suppresses interference. In VERITAS, it is an FPGA telescope trigger with time alignment, narrow coincidence gating, and image-moment capability. In radio astronomy, it is a GPU-accelerated statistical detector that either sparsely invokes SOFIA 2 or operates in the image-frequency domain to exploit periodicity (Liu et al., 12 Feb 2025, Schwab et al., 2024, Zitzer, 2013, Li et al., 26 Sep 2025).

The limitations are likewise domain-specific. In the MRPC system, thresholds, coincidence windows, baseline limits, and oscillation limits are tuned from waveform characteristics and waveform-library statistics, so performance depends on calibration. In CT5TEA/CTC, the abstract and detailed summary report slightly different threshold and noise figures, and the trigger path is optimized around analog sums rather than full waveform classification. In VERITAS, the topological image-moment trigger is described as a future capability rather than an already deployed mode. In radio FITrig, the image-frequency branch incurs the extra FFT cost $>1.4\,\mathrm{GHz}$18, while FIP-TOI identifies static tile size, fixed threshold, corner clipping of up to approximately 8.6%, and the absence of deconvolution as explicit limitations. The comparative results nonetheless converge on a consistent technical role for FITrig: reducing false triggers or false positives, constraining bandwidth or compute, and preserving enough temporal or spatial information to support localisation rather than mere event counting (Schwab et al., 2024, Zitzer, 2013, Li et al., 26 Sep 2025, Li et al., 6 Dec 2025).