Dynamic Merge Point Prediction (DMPP)

• Dynamic Merge Point Prediction (DMPP) is a hardware technique that dynamically identifies and exploits control-flow merge points to recover from branch mispredictions without a full pipeline flush.
• It leverages wrong-path buffering, merge point detection, and a predictor table update mechanism to reduce mispredictions by 43% MPKI and replace 58% of error-prone branch predictions.
• DMPP employs a confidence-cost policy to selectively target high-risk branches, achieving significant performance gains with minimal hardware overhead (~2.8 KB).

Dynamic Merge Point Prediction (DMPP) is a hardware technique for mitigating performance penalties from hard-to-predict conditional branch mispredictions by dynamically detecting and exploiting control-flow reconvergence (“merge points”) at runtime. DMPP operates by leveraging instructions on the wrong-path after a misprediction and tracking control-flow until the actual merge point with the correct path is observed, enabling precise recovery without a full pipeline flush. Incorporating a confidence-cost system allows DMPP to target only branches where merge-point prediction is likely to reduce penalty, yielding substantial improvements in misprediction rate and overall processor performance (Pruett et al., 2020).

1. Runtime Algorithm and Merge Point Detection

The DMPP mechanism executes the following sequence when a branch misprediction occurs:

1. Wrong-Path Buffering: On detection of a misprediction, all instructions after the branch in the Reorder Buffer (ROB), up to a maximum window (100 dynamic instructions), are copied into a Wrong-Path Buffer (WPB). For each instruction, the system tracks its dynamic distance from the branch and accumulates a bit-vector representing destination registers written by wrong-path instruction stream.
2. Merge Point Identification: After flushing the pipeline and redirecting fetch down the correct branch path, the system probes WPB entries as correct-path instructions retire. A match between a retiring instruction’s PC and a valid WPB entry indicates the execution point where correct and wrong paths reconverge—the merge point. Both the wrong-path and correct-path instruction distances and their register write sets are consolidated.
3. Predictor Table Update: A new entry is created in the Merge Point Predictor Table for the originating branch, storing the merge-point PC, the (maximum) merge distance, and the union of independent-register sets (bitwise OR of path register vectors).
4. Prediction and Validation: On subsequent encounters with the same branch, under the confidence-cost policy (see Section 3), the system retrieves merge-point prediction attributes. When the branch retires, an update-list entry monitors correct-path instruction retirement up to the predicted merge distance. If the predicted merge-point PC occurs within distance and no unexpected register writes are observed, the confidence counter for the predictor entry is incremented; otherwise, it is decremented.

Accuracy Formula: $$\text{Accuracy (\%)} = \frac{\#\text{CorrectMergePredictions}}{\#\text{BranchInst}}\times 100\%$$ where $\#\text{CorrectMergePredictions}$ is the number of successful merge-point predictions matching within distance and with register independence, and $\#\text{BranchInst}$ is the total dynamic instances where DMPP was applied (Pruett et al., 2020).

Pseudocode (selection):

def mergePointDetect(branchPC): WPB.invalidateAllEntries() for inst in ROB after branchPC up to MAX_DIST: WPB[inst.PC] = { 'wrongDist': inst.ordinal - branch.ordinal, 'wrongRegs': union(wrongRegs, inst.dstRegs) } WPB.tag, WPB.valid = branchPC, True def onRetire(correctInst): for WPB entry tagged by branchPC: if correctInst.PC == branchPC or age > MAX_DIST: invalidate WPB entry elif correctInst.PC in WPB: # Merge point found insert into PredictorTable(branchPC, ...) invalidate WPB entry

2. Hardware Microarchitecture and Storage Cost

DMPP introduces three main hardware data structures, all modest in size:

• Merge Point Predictor Table: 128 entries, 4-way set-associative. Each stores a 35-bit merge-PC, 7-bit merge-distance, 32-bit independent-register bit-vector, and 3-bit confidence counter (≈1.6 KB total).
• Wrong-Path Buffer (WPB): 128 entries, 4-way set-associative with LRU replacement. Each entry records the used flag, branchPC tag, path distances, and register bit-vectors for both wrong and correct paths (≈1.0 KB).
• Update List: 8 entries, fully-associative. Monitors update of predictor confidence on retirement (≈113 bytes).

All predictor-table lookups are performed in parallel with the BTB and main branch predictor on instruction fetch. WPB is accessed on correct-path instruction retire to detect merge points. Update List fits within a single retire cycle.

Storage Overhead Summary:

Structure	Entries	Size
Merge Point Predictor Table	128 × 4-way	~1.6 KB
Wrong-Path Buffer (WPB)	128 × 4-way	~1.0 KB
Update List	8	~113 bytes
Total	—	~2.8 KB

WPB is sized to copy up to 100 wrong-path instructions per misprediction, with latency hidden by pipeline flush and pipeline refill operations (Pruett et al., 2020).

3. Confidence-Cost Policy and Control Independence

DMPP is selectively applied only to branches identified as "hard-to-predict" based on per-branch confidence and dynamic penalty (cost):

• Confidence: Extracted from the 3-bit prediction counter of the highest-matching TAGE predictor component, with an override from the JRS high-confidence detector. Thresholds are:
  • Conf-Low: weakly-taken or weakly-not-taken
  • Conf-Med: otherwise, unless JRS signals high confidence
  • Conf-High: JRS high-confidence match
• Cost: Average dynamic resolution latency for each branch is tracked in a Branch Latency Table using exponential smoothing:

$$L_{\rm new} = 0.9 \times {\rm latency}_{\rm measured} + 0.1 \times L_{\rm old}$$

If $L_{\rm new} > 50$ cycles, cost is Lat-High; otherwise, Lat-Low.

• Decision Logic: Branches are categorized into 6 buckets. Merge-point prediction is only invoked for high-penalty or low-confidence branches, as shown below:

	Lat-Low	Lat-High
Conf-Low	MP	MP
Conf-Med	BP	MP
Conf-High	BP	BP

Only the “MP” cells use merge-point prediction; others continue to use conventional branch prediction.

4. Empirical Evaluation

DMPP was evaluated on a cycle-accurate x86 simulator (Multi2Sim front end, custom back end) with a 4-wide issue, 512-entry ROB, and 64 KB TAGE branch predictor. Benchmarks were drawn from SPEC CPU2006 Integer suite, using SimPoint sampling.

Key results:

Metric	Value
DMPP accuracy	95 %
WPB false negatives	< 1 %
Mispredictions replaced	58 %
Branch-only MPKI	4.2
DMPP (MPP) MPKI	2.4
Max committed distance	100 instructions
Storage overhead	2.8 KB

DMPP replaces 58% of all branch mispredictions with correct merge-point predictions, attaining a 43% reduction in mispredictions per kilo-instruction (MPKI) over baseline branch prediction (Pruett et al., 2020). The average overprediction of merge distance is 23 instructions (basic MPP) or 37 (with UPDATE_MAX policy).

5. Comparative Analysis and Limitations

Comparison with the infinite-size reconvergence predictor of Collins et al. under analogous measurement standards reveals that the infinite-size model, when adjusted for nontrivial merge points, achieves 78% accuracy, whereas DMPP attains 95% accuracy with practical (<4 KB) hardware cost. Moreover, DMPP replaces 51% more mispredictions (58% vs. 38%) than the infinite-size model (Pruett et al., 2020).

UPDATE_MAX Policy: This policy grows the stored merge distance to the maximum observed, raising accuracy by about 14%. However, this increases over-reservation of instruction-window resources (average 37 vs. 23 instructions).

Failure Modes and Trade-offs:

• <1% of WPB opportunities are lost to evictions (missed merge entries).
• Overestimation of merge distance temporarily holds extra resources under optimistic assumptions of register independence.
• 5% prediction failure rate: an incorrect DMPP result triggers a full pipeline flush, counted as a misprediction.
• DMPP is disabled for trivial merge-point cases (e.g., simple loops or calls) as determined by decision logic.

The approach yields high MPKI reduction by targeting only risky branches, leveraging dynamic runtime detection instead of static compiler heuristics, and achieving high-accuracy merge-point detection.

6. Significance and Implications

DMPP represents a hardware-only, lightweight (about 2.8 KB) mechanism for dynamically locating post-misprediction control-flow merge points, activating only for candidates with both high penalty and low directional predictability. The methodology demonstrates that a significant portion of remaining difficult-to-predict branches can be mitigated via dynamic merge-point prediction, delivering substantial overall performance improvements in superscalar out-of-order processors. A plausible implication is that control-independence techniques, when combined with nuanced confidence and cost management, offer a tractable and efficient path to reducing the persistent impact of unpredictable branches in practical high-performance CPU designs (Pruett et al., 2020).