Electromagnetic Fault Injection (EMFI)

• EMFI is a noninvasive technique that uses targeted electromagnetic fields to induce faults in microelectronic circuits, enabling research on hardware vulnerabilities.
• It exploits Faraday's law to generate precise voltage spikes that disrupt instruction flow, data handling, and sensor feedback across various devices.
• EMFI research drives both offensive attack strategies and defensive countermeasures, advancing secure boot, cryptographic integrity, and fault mitigation methods.

Electromagnetic Fault Injection (EMFI) is a noninvasive and highly precise physical attack methodology that leverages rapidly varying electromagnetic fields to induce transient faults in microelectronic circuits. EMFI has been extensively utilized to corrupt instruction flow, data path, or analog sensor feedback in both legacy microcontrollers and complex modern SoCs, threatening the integrity of cryptographic implementations, secure boot logic, device authentication, and closed-loop control systems. Due to its spatial and temporal locality, EMFI remains a uniquely powerful tool for both offensive and defensive hardware security research.

1. Physical Principles and Coupling Mechanisms

EMFI exploits Faraday’s law of induction. A pulsed or high-frequency current through a coil probe generates a time-varying magnetic flux density $\mathbf{B}(t)$, which induces a voltage $$V_{\text{ind}}(t) = -\frac{d\Phi(t)}{dt} = -\frac{d}{dt} \iint_{A} \mathbf{B}(t) \cdot d\mathbf{A}$$ across on-chip loops (interconnects, rails, or sensors) (Joy et al., 22 Nov 2024, Moro et al., 2014). The induced voltage is a function of the magnetic field gradient, mutual inductance $M$ of coil and victim, and the rise/fall time of the injected pulse.

In typical EMFI setups, the probe is positioned $\sim$0.1–0.5 mm above the package, aligned with critical power, clock, or signal domains (2407.6019, Trouchkine et al., 2019, Kühnapfel et al., 2022). The spatial decay of induced field strength is rapid, with $B(r) \sim \mu_0 I / (2\pi r)$, and the coupling coefficient $k = M/\sqrt{L_\text{probe} L_\text{victim}}$ governs injection efficiency (Trouchkine et al., 2019).

On analog or sensor feedback lines (e.g., power converter sensor loops), the incident $E(t)$ field is demodulated by nonlinearities, producing persistent DC offsets; for digital logic, sub-nanosecond timing is required to align the glitch with the circuit’s setup/hold or latch windows (Szakály et al., 2023).

2. Experimental Platforms and Parameterization

EMFI systems integrate a programmable pulse generator (tens to hundreds of volts, nanosecond-scale rise/fall times) and a small near-field coil probe (typically 0.5–2 mm diameter, ferrite-cored for focused flux) on a precision XYZ translation stage (Kühnapfel et al., 2022, Rivière et al., 2015, Moro et al., 2014). Automated setups achieve sub-10 µm repeatability and are scalable from microcontrollers to full package SoCs (Kühnapfel et al., 2022).

Table: Representative EMFI Parameter Ranges

Parameter	Typical Range	Notes
Pulse amplitude, $V$	±100–500 V	Higher $|V|$ increases set-1 bias/area affected
Pulse width, $\Delta t$	1.5–1000 ns	1.5–10 ns for digital logic; up to $\mu$s for analog
Rise/fall time	≈2 ns (as low as 200 ps)	Sets edge sharpness; critical for cache/fetch attack
Probe–die distance, $d$	0.1–0.7 mm	Strong spatial dependence; optimal via cartography
Timing jitter	<5 ps (intrinsic), <3 ns (system)	Essential for reproducibility at high f$_{\text{clk}}$
Positioning grid	0.5–1 mm step (SoC), 20µm (MCU)	Used to identify “hot spots”

Control and monitoring typically use GPIO/trigger signals from test firmware, high-speed oscilloscopes for pulse/response validation, and JTAG/UART for result extraction (Rivière et al., 2015, Singh et al., 2022).

3. Fault Models and Induced Behaviors

Fault manifestations in EMFI span a spectrum determined by the electrical/architectural context of the disturbed operation.

Instruction fetch/decode faults are prevalent in slow-Flash-based MCUs, where the EM pulse overlaps with bus fetch or decode windows, yielding single-instruction skips, opcode replacements, or exceptions; the output Hamming weight increases with $|V|$ due to set-1 bias (Moro et al., 2014, Moro et al., 2014). In high-speed SoCs, pulse alignment with instruction or L1I cache refill induces sticky instruction skips or persistent instruction word corruption (Trouchkine et al., 2019, Rivière et al., 2015).

Data-path faults comprise bit flips or multi-bit “set-1” faults associated with data fetches, especially from off-chip or slow memories during LDR-type instructions, often modeled as $f^{(\text{set1})}_I(x) = x \vee M_I$ for affected bit mask $M_I$ (Moro et al., 2014).

Cache and microarchitectural faults in complex SoCs include instruction-cache refill faults (“4-skip + 4-replay” model), L2 block relocations, and MMU page-table entry (PTE) bit-flips or address remapping (e.g., $PT\_entry' = PT\_entry \oplus S$ for a shift mask $S$) (Rivière et al., 2015, Trouchkine et al., 2019).

Special subsystem faults are enabled by EMFI on sensor feedback in power conversion devices, causing $\sim$1–2% output voltage/control errors or catastrophic battery damage via spoofed sensor DC offset $\Delta V_{\rm attack} \propto {P_T}/{d^2}$ (Szakály et al., 2023).

Side-channel and message injection faults have been demonstrated on differential signaling buses (CAN, USB, HDMI) via common-mode field injection, enabling up to 90% bit-flip rates for optimal RF frequency/amplitude (Zhang et al., 2022).

4. Case Studies: EMFI in Embedded Systems and Secure Processors

Microcontrollers: Classical experiments on Cortex-M3 at 56 MHz with 10 ns, ±200 V pulses document nearly 100% corruption at fetch/decode timing windows; statistical models parameterize bit flip/skew probabilities as functions of $(V_p, \Delta t, t_i)$, facilitating predictive attack development (Moro et al., 2014).

Instruction cache attacks: On ARMv7-M, near-cycle-precise 1.5 ns pulses induce high-probability ($\sim$96%) “4-skip + 4-replay” instruction-cache faults within a ~2 ns window of the cache-refill period, bypassing multiple-instruction skip countermeasures and enabling one-shot DFA, BellCoRe CRT-RSA, and unmasking attacks (Rivière et al., 2015).

Trusted Execution Environments: EMFI allows privilege escalation and bypass of secure boot, range-check, or cryptographic checks in ARM TrustZone, QSEE, or AMD-SP platforms. Critical events include bit flips in secure memory, instruction-skips in control logic, TLB/caches corruption, and register value faults (Joy et al., 22 Nov 2024, Kühnapfel et al., 2022). For AMD-SP, 500 V, 73 ns pulses at 0.1 mm lift-off, precisely timed to the signature-compare event, skip the conditional branch to boot/halt with a 22% success rate over $10^4$ attempts (Kühnapfel et al., 2022).

Memory authentication bypass: For eMMC Replay Protected Memory Block (RPMB), $200$ V, $100$ ns pulses injected at ±10 ns within a $0.6\,\mu$s “HMAC-check” window can skip single instructions in the comparison loop, allowing arbitrary RPMB writes with no effect on user data, at a success rate as high as 2% per attempt (Fukami et al., 27 Nov 2025).

Clock frequency dependence: EMFI attack success probability $P_\text{success}$ increases monotonically with processor clock frequency $f_\text{clk}$, as shorter clock periods reduce timing margins and increase susceptibility. A plausible implication is that dynamic frequency scaling or coarse clock jitter can significantly lower $P_\text{success}$ (Koffas et al., 2023).

5. Countermeasures and Mitigation Strategies

Countermeasures are multi-layered, tailored to attack primitives and the underlying hardware/software.

Hardware-level:

• Spatial hardening: On-die/domain EM shielding (Faraday cages or $\mu$-metal), minimizing mutual inductance and attenuating stray fields (Kühnapfel et al., 2022, Joy et al., 22 Nov 2024).
• Redundant logic/datapath: Dual-rail or duplicated execution for signature and control flow checks; parity/ECC on buses; error-detecting codes for cache lines (Trouchkine et al., 2019).
• On-die sensors: Ring-oscillator or LC-tank devices to detect transient field/voltage spikes, activating reset or secure shutdown if threshold exceeded ($\sim$99% detection for $\geq$300 V/10 ns) (Joy et al., 22 Nov 2024).
• Clock/supply domain management: Dynamic frequency scaling, clock jitter/randomization, decoupling capacitors, and hardened localized supply (Koffas et al., 2023).

Software-level:

• Temporal redundancy (triplication): Triplicate sensitive instructions, aligning copies to avoid single fetch overlap; triplication reduces fault coverage to $<1\%$ from baseline $>20\%$ under optimal EMFI (Moro et al., 2014).
• Duplication + compare: Duplicate critical operations with compare/branch error handlers; robust to instruction/data-path faults except for tightly packed instructions (if both are affected, undetectable) (Moro et al., 2014).
• Bit-slicing redundancy: For cryptographic kernels (e.g., Dilithium NTT), intra-register duplication and lockstep operation detect $>60\%$ of exploitable EMFI-induced faults in practice, with a $49\times$ performance and $2.1\times$ code-size overhead (Singh et al., 2022).
• Control flow and integrity checks: Canaries, checksums, and runtime validation of counters/branches (Koffas et al., 2023).

Protocol-level:

• Authentication, MAC, and error-coding: For memory and bus transactions, utilize constant-time compare and multi-round authentication, raising Hamming-weight for “pass” constants or interleaving redundant verification (Fukami et al., 27 Nov 2025, Zhang et al., 2022).

Analog/sensor protection:

• Faraday-cage enclosure, RF filter stages, sensor line redundancy, and real-time challenge/response verification. Simple envelope detectors alert to suspicious $>$MHz EM events (Szakály et al., 2023).

6. Measurement, Calibration, and Attack Optimization

High-precision EMFI requires extensive calibration and statistical analysis. Effective attack campaigns iterate over spatial grids, timing offsets, pulse amplitudes and widths—with up to $10^4$ injections per target window—recording outcome distributions (e.g., skip, set-1, crash, unaffected) (Rivière et al., 2015, Kühnapfel et al., 2022). Temporal alignment error $<3$ ns RMS is attainable; spatial repositioning error $<10$ μm over 50 mm is demonstrated for advanced SoC rigs (Kühnapfel et al., 2022).

Peak fault windows typically span 1–3 ns for instruction-cache refill, $0.6\,\mu$s for HMAC comparison, or $\sim100$ ns for data fetch, depending on subsystem and platform (Fukami et al., 27 Nov 2025, Rivière et al., 2015, Trouchkine et al., 2019). Attack optimization involves identifying “hot spots” through coarse then fine grid scanning, followed by parametric sweeps in the aligned window.

7. Future Directions and Security Implications

EMFI continues to expose new attack surfaces in high-performance SoCs, analog feedback systems, and secure architectures. Integration of microarchitectural fault models in proofs for OS/hypervisor security is needed (Trouchkine et al., 2019). Enhanced co-design between hardware/package/board shielding, dynamic multi-layer detection, and continuous EMFI-driven certification testing (<$10^{-8}$ success rate per critical function) are required for robust future TEEs and critical infrastructure (Joy et al., 22 Nov 2024).

Despite advances in countermeasures, no single protection is fool-proof; attackers can leverage timing, spatial focus, and system-specific vulnerabilities. Security engineers must employ holistic, defense-in-depth strategies, continuous red-team evaluation, and adherence to updated threat models calibrated with state-of-the-art EMFI capabilities.