Parametrically Driven iSWAP Gate Using a Capacitively Shunted Double-Transmon Coupler at the Zero-Flux Sweet Spot

Abstract: A double-transmon coupler (DTC) enables a fast, high-fidelity CZ gate between two highly detuned, fixed-frequency transmon qubits. Moreover, a recently proposed capacitively shunted DTC (CSDTC) realizes a small residual ZZ interaction over a wide flux-bias range around zero flux, eliminating the necessity of static flux biasing while maintaining high CZ-gate fidelity. However, CZ gates with the DTC and CSDTC require baseband flux pulses with large amplitudes, which are vulnerable to pulse distortion and decoherence due to large qubit-coupler hybridization. To address these issues, we experimentally demonstrate a parametrically driven iSWAP gate operated at zero flux bias between highly detuned, fixed-frequency transmon qubits coupled through a CSDTC. Using a simple flux-drive waveform without predistortion, we realize an average gate fidelity of 99.92(2)% at a total gate time of 112 ns. The observed high-fidelity performance is consistent with small qubit-coupler hybridization and small effective ZZ interaction during the gate. Our numerical simulations reproduce the experimentally observed iSWAP interaction rate and effective ZZ interaction, demonstrating the applicability of the theoretical model not only to spectral information but also to time-domain dynamics such as gate operations. These results boost further progress in the research of superconducting quantum computers.

• The paper demonstrates a parametrically driven iSWAP gate that achieves 99.92% fidelity by suppressing residual ZZ interactions using a capacitively shunted double-transmon coupler.
• The study employs a second-harmonic AC flux drive with a smooth tanh-profile envelope and full multi-mode Hamiltonian simulations for accurate gate characterization.
• The findings reveal reduced calibration overhead and minimal leakage, highlighting the potential for scalable, high-coherence operations in fixed-frequency superconducting circuits.

Parametrically Driven iSWAP Gate Using a Capacitively Shunted Double-Transmon Coupler at the Zero-Flux Sweet Spot

Introduction and Motivation

Two-qubit entangling gates with high fidelity and speed underlie fault-tolerant quantum computation using superconducting circuits. Fixed-frequency transmon architectures benefit from improved noise resilience, but efficient tunable coupling is mandatory to overcome the limitations posed by residual $ZZ$ interactions and decoherence during gate operations. The capacitively shunted double-transmon coupler (CSDTC) advances the double-transmon coupler (DTC) framework by achieving effective suppression of static $ZZ$ interactions over a broad flux range centered at zero flux bias. This work introduces the first experimental realization of a parametrically driven iSWAP gate at the CSDTC's zero-flux sweet spot, addressing long-standing challenges in gate calibration overhead and decoherence associated with large flux excursions.

Figure 1: Device and operating principle of the parametrically driven iSWAP gate at the zero-flux sweet spot.

Device Architecture and Operating Principle

The device comprises two widely detuned, fixed-frequency transmon qubits (Q1 and Q2) coupled via a CSDTC. The coupler's internal P and M modes are hybridizations of two transmons, engineered for strong tunability of the M-mode's frequency with flux, while the P-mode remains relatively static. The CSDTC's architecture ensures that the residual $ZZ$ interaction is minimized and remains nearly flat over a significant flux interval around zero, efficiently suppressing coherent $ZZ$ errors both at idle and during gate operations.

Parametric activation of the iSWAP is achieved by applying a resonant AC flux drive at half the qubit–qubit detuning to the coupler loop. The quadratic flux dependence of the M-mode frequency enables second-harmonic modulation, which mediates an exchange between the $\ket{01}$ and $\ket{10}$ states. This approach confines the quantum state evolution to the computational subspace and eliminates the need for static flux offsets, unlike first-order parametric protocols.

iSWAP Gate Characterization

Gate Calibration, Dynamics, and Benchmarking

The iSWAP gate is implemented with a smooth, tanh-profile envelope modulating the sinusoidal AC flux. The total gate time, including $12\,\mathrm{ns}$ of idling, is $112\,\mathrm{ns}$. The simple analytical waveform employed obviates the requirement for predistortion corrections, drastically simplifying calibration. Phase errors induced by ac Zeeman shifts and exchange-axis misalignment are compensated by systematic frame tracking—virtual-Z rotations and phase updates for both qubit and coupler control oscillators.

Direct characterization of the iSWAP interaction demonstrates expected chevron patterns in population transfer as a function of flux modulation amplitude and frequency.

Figure 2: Characterization of parametrically driven iSWAP interaction; chevron patterns and extracted exchange rates as functions of drive amplitude.

Randomized benchmarking (RB and leakage RB) is employed to quantify gate performance. An average gate fidelity of $99.92(2)\%$ is reported for the $112\,\mathrm{ns}$ iSWAP, corresponding to a gate error of $ZZ$0. Leakage error is suppressed to $ZZ$1, and the total infidelity is primarily limited by incoherent processes.

Figure 3: Randomized benchmarking results for the iSWAP gate, showing sequence fidelity decay and negligible leakage.

Error Mechanisms and Incoherent Limits

The error analysis isolates three principal contributions: coherent $ZZ$2 error, leakage, and incoherent relaxation/dephasing. The coherent $ZZ$3 error remains quadratic in the accumulated phase and is efficiently mitigated using calibrated virtual-Z frame updates. Leakage is minimal, even as drive amplitude increases, as verified both experimentally and in full Hamiltonian simulations.

Figure 4: iSWAP depolarization-induced error, $ZZ$4 error, and leakage versus gate duration, alongside extrapolated error limits from measured coherence times.

The primary constraint on fidelity is incoherent error accumulated over the gate duration. Effective coherence times during operation ($ZZ$5) are quantitatively extracted and displayed to be systematically longer for the iSWAP gate (approximately $ZZ$6s) compared to CZ implementations, which require substantially greater hybridization with short-lived coupler modes.

Figure 5: (a) Optimized flux-drive waveform for the iSWAP gate versus symmetric net-zero flux pulse for CZ. (b) Simulated coupler hybridization showing reduced participation during iSWAP.

Suppression of $ZZ$7 Interaction: Static and Dynamical Contributions

Through direct measurement and simulation, the effective $ZZ$8 interaction during iSWAP operation is demonstrated to be suppressed below its static value due to a dynamical, drive-induced component that partially cancels the static contribution. The CSDTC's unique flux response further amplifies this effect by providing wide flux intervals with minimal static $ZZ$9, and the dynamical term takes a positive value under second-harmonic drive, nearly nullifying the total $ZZ$0 error at optimal amplitude.

Figure 6: (a) Pulse sequence for effective $ZZ$1 evaluation, (b) measured and simulated effective $ZZ$2 interaction as a function of drive strength. Inset: decomposition of static and dynamical contributions.

Agreement with Full-Device Modeling

Theoretical predictions using the full multi-transmon Hamiltonian in the Cooper-pair basis yield quantitative agreement with experimental data for static spectra, iSWAP/exchange rates, effective/dynamical $ZZ$3, and hybridization fractions throughout the full dynamical modulation protocol. The analytic models using the lowest-order perturbative expansion remain accurate at modest drives; full numerics are required for strong-drive corrections.

Figure 7: Comparison of experimental and simulated iSWAP rate and dynamical $ZZ$4 as a function of flux-drive amplitude.

Experimental System and Readout Infrastructure

The measurement and control architecture employs high-fidelity room-temperature electronics (ZH Instruments SHFQC+, HDAWG) and attenuation/thermalization at all cryostat stages, with high SNR single-shot readout employing a near-quantum-limited IMPA followed by HEMT amplification. State discrimination leverages k-means clustering in the IQ plane to account for leakage and spurious state assignments, and assignment fidelities for both data qubits and coupler modes exceed $ZZ$5.

Figure 8: Room-temperature control electronics and cryogenic wiring for all lines relevant to data qubits and coupler flux/crosstalk.

Figure 9: Q1, Q2 single-shot readout IQ distributions and cluster centers, showing assignment clusters with leakage discrimination.

Implications and Outlook

This demonstration establishes second-harmonic parametric iSWAP gates at the CSDTC zero-flux sweet spot as a viable route for high-fidelity, low-overhead two-qubit gates in architectures based on fixed-frequency transmons. The results show that both coherent and leakage errors can be suppressed to negligible levels, with remaining infidelity dominated by incoherent relaxation and dephasing processes—ultimately set by the qubit's intrinsic $ZZ$6 and $ZZ$7. The drastically reduced hybridization with lossy coupler modes and softer flux excursions compared to baseband-activated CZ gates mark substantial practical advantages.

The formalism for full-Hamiltonian, multi-mode simulation aligns closely with experimental data across both static and dynamic observables, endorsing the applicability of these techniques for predictive gate optimization in next-generation superconducting quantum computers. Adjustments in drive waveform, pulse shaping, and multi-tone protocols could offer further reductions in dynamical $ZZ$8 and high-amplitude dephasing. Expanding these methods to multi-qubit coupler networks, leveraging ac sweet spots, or integrating multi-tone cancellation of sideband-induced $ZZ$9 represents promising directions for theoretical and device-level advances.

Conclusion

The experimental realization and systematic analysis of a parametrically driven iSWAP gate using a capacitively shunted double-transmon coupler at the zero-flux sweet spot provides compelling evidence for the practicality of high-coherence, low-complexity, and high-fidelity entangling operations in fixed-frequency circuit QED architectures. The suppression of coherent errors, minimal calibration overhead, and validation of numerical design frameworks highlight this approach as a strong candidate for scalable, error-corrected superconducting quantum information processors.

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