Dolan Junctions for Superconducting Qubits

• Dolan junctions are self-aligned Josephson tunnel junctions formed via a bilayer resist shadow evaporation process that defines precise qubit parameters.
• Their fabrication leverages controlled oxidation and geometry-aware corrections to minimize junction variability and improve yield across wafer-scale processes.
• Stress-relief design modifications and process optimizations enhance mechanical stability and uniformity, making these junctions scalable for advanced superconducting circuits.

Searching arXiv for recent and foundational papers on Dolan-bridge Josephson junctions to ground the article. Dolan junctions are Josephson tunnel junctions defined by shadow evaporation through a suspended resist bridge, conventionally the Dolan bridge, in an $\mathrm{Al/AlO_x/Al}$ process widely used for superconducting qubits. In the standard self-aligned implementation, a bilayer resist is patterned so that development leaves a narrow suspended span; double-angle evaporation then deposits two aluminum electrodes whose overlap beneath the bridge defines the junction area and, after oxidation, the tunnel barrier (Skinner-Ramos et al., 1 Feb 2025). Within superconducting quantum information hardware, the term is most commonly associated with this fabrication geometry rather than with unrelated uses of “Dolan” in higher category theory or integrable systems. The defining technical themes are self-alignment, sub-micron shadow masking, and the strong coupling between lithographic geometry, oxidation conditions, and junction-level variability in critical current, yield, and qubit-frequency reproducibility (Moskaleva et al., 2024).

1. Definition and fabrication principle

A Dolan junction is formed using a bilayer resist stack and shadow evaporation. In the standard formulation summarized for $\mathrm{Al/AlO_x/Al}$ qubit junctions, a bilayer of MMA (bottom) and PMMA (top) is patterned by e-beam lithography; development undercuts the MMA, leaving a narrow suspended PMMA span, the Dolan bridge; the sample is then metalized by double-angle evaporation: deposit the first Al layer normal to the surface, oxidize it to form a thin $\mathrm{AlO_x}$ tunnel barrier, and deposit the second Al layer at an angle (Skinner-Ramos et al., 1 Feb 2025). The overlap of the two angled Al films under the shadow of the bridge defines the Josephson junction.

This self-aligned method is used because it is relatively simple and can produce small, aligned junctions needed for qubits (Skinner-Ramos et al., 1 Feb 2025). A closely related variant, the Dolan–Niemeyer-Bridge geometry, preserves the same shadow-mask principle while using optical direct-write photolithography rather than e-beam lithography (Monroe et al., 2021). In that implementation, the authors use an all-optical $375\ \mathrm{nm}$ direct-write lithography system, a bilayer resist stack of LOR 10B and Shipley S1805, and a double-angle aluminum evaporation sequence of $30\ \mathrm{nm}$ at $+45^\circ$, oxidation, and $60\ \mathrm{nm}$ at $-45^\circ$ (Monroe et al., 2021).

The role of the junction in transmon circuits follows the conventional Josephson-energy and charging-energy relations

$$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$

with the critical current commonly estimated from the Ambegaokar–Baratoff relation

$I_c = \frac{\pi \Delta}{2eR_n},$

where the superconducting gap of Al is given as $\mathrm{Al/AlO_x/Al}$0 in one of the cited fabrication studies (Skinner-Ramos et al., 1 Feb 2025). In this sense, Dolan junctions are not merely a lithographic artifact: they are the nonlinear element that sets the Josephson energy and therefore directly influence qubit frequency and anharmonicity (Moskaleva et al., 2024).

2. Resist architecture, evaporation geometry, and effective junction formation

The resist architecture is central to the operation of a Dolan junction because the suspended bridge acts as a shadow mask during angled deposition. In planar qubit fabrication, the technique is typically implemented with bilayer resists and standard Al–AlOx–Al double-angle shadow evaporation, but the exact stack differs by process. One comparative study uses Dolan junctions with a $\mathrm{Al/AlO_x/Al}$1 PMGI SF7 support layer followed by $\mathrm{Al/AlO_x/Al}$2 PMMA 950K A3, with evaporation tilt $\mathrm{Al/AlO_x/Al}$3, azimuth angles $\mathrm{Al/AlO_x/Al}$4, and deposition thicknesses of $\mathrm{Al/AlO_x/Al}$5 bottom and $\mathrm{Al/AlO_x/Al}$6 top, with static oxidation at $\mathrm{Al/AlO_x/Al}$7 for $\mathrm{Al/AlO_x/Al}$8 (Muthusubramanian et al., 2023). Another uniformity study treats Dolan-bridge double-angle deposition on Si chips using PMGI/ZEP resist, Al thicknesses spanning roughly $\mathrm{Al/AlO_x/Al}$9, and evaporation angles mainly $\mathrm{AlO_x}$0 and $\mathrm{AlO_x}$1, with dynamic oxidation at $\mathrm{AlO_x}$2 for $\mathrm{AlO_x}$3 and sample rotation during oxidation (Kakuyanagi et al., 29 May 2026).

The effective overlap geometry is not determined solely by the designed mask dimensions. The cited literature attributes systematic deviations to shadow evaporation geometry, finite source size, sidewall deposition, and position-dependent evaporation angle across the wafer (Moskaleva et al., 2024). This is why wafer-scale reproducibility studies model the actual junction area using geometry-aware corrections rather than the nominal lithographic overlap alone. One paper expresses this through a Shadow Evaporation Bias Correction model that incorporates top and bottom resist thickness, substrate-holder tilt angle, crucible-to-substrate-holder distance, wafer position $\mathrm{AlO_x}$4, evaporation-angle variation, and finite source geometry (Moskaleva et al., 2024).

A subtle but important point arises in the optical direct-write Dolan–Niemeyer-Bridge implementation. With $\mathrm{AlO_x}$5 evaporation and the reported oxidation sequence, the process creates two junctions: a side-face junction formed on the bottom-electrode sidewall and a top-face junction formed on the top surface (Monroe et al., 2021). Because the side-face junction is approximately $\mathrm{AlO_x}$6, it is comparable to conventional nanofabricated junctions despite the large lithographic overlap, whereas the top-face junction is much larger and, when filler layers are used, has a thicker oxide. The paper estimates the large thick junction contributes only about $\mathrm{AlO_x}$7 participation, implying that the circuit response is dominated by the thin side-face junction (Monroe et al., 2021). This suggests that lithographic area and effective tunneling area need not coincide in Dolan-style geometries.

3. Mechanical fragility of the Dolan bridge

A major practical limitation of conventional Dolan fabrication is mechanical fragility during resist development. The nanoscale suspended bridge is described as “fragile and notoriously prone to fracture” in a conventional PMMA/MMA process at room temperature, with failures observed nearly $\mathrm{AlO_x}$8 of the time during development for standard self-aligned masks (Skinner-Ramos et al., 1 Feb 2025). The same study attributes the failure primarily to large intrinsic lateral stress after development.

That work independently measured deposition-induced stress in the resist layers as about $\mathrm{AlO_x}$9 for MMA and about $375\ \mathrm{nm}$0 for PMMA, and notes that the intrinsic lateral stress in the bridge without stress-relief channels exceeds the reported PMMA tensile strength at room temperature of about $375\ \mathrm{nm}$1 (Skinner-Ramos et al., 1 Feb 2025). The authors used COMSOL finite-element simulations of the Dolan bridge domain with material properties taken from measurement and found that the bridge in the no-channel design experiences stress high enough to exceed the PMMA tensile strength (Skinner-Ramos et al., 1 Feb 2025).

The proposed remedy is a modified junction mask that adds stress-relief channels on both sides of the bridge. For the simulated and fabricated devices, the geometric parameters were $375\ \mathrm{nm}$2, $375\ \mathrm{nm}$3, and $375\ \mathrm{nm}$4 varied from $375\ \mathrm{nm}$5 to $375\ \mathrm{nm}$6 in $375\ \mathrm{nm}$7 steps; the stress-relief channels were $375\ \mathrm{nm}$8 wide, $375\ \mathrm{nm}$9 long, placed equidistant from the bridge, with channel-to-bridge spacing swept from $30\ \mathrm{nm}$0 to $30\ \mathrm{nm}$1 (Skinner-Ramos et al., 1 Feb 2025). The main simulation result is that adding stress-relief channels reduces the lateral stress in the Dolan bridge by more than $30\ \mathrm{nm}$2 for all bridge geometries studied. With channels placed at about $30\ \mathrm{nm}$3 from the bridge, the induced stress drops to about $30\ \mathrm{nm}$4 of the PMMA tensile strength, and for all $30\ \mathrm{nm}$5 the intrinsic stress is reduced to roughly $30\ \mathrm{nm}$6 of the stress in the no-channel design (Skinner-Ramos et al., 1 Feb 2025). When channels are farther away, around $30\ \mathrm{nm}$7 or more, the stress approaches the PMMA tensile limit again.

Experimentally, the reported yield improvement is decisive: conventional Dolan bridges made with PMMA/MMA at room temperature failed nearly $30\ \mathrm{nm}$8 of the time during development, whereas the stress-relief channel mask enabled fabrication of over $30\ \mathrm{nm}$9 Josephson junctions with no fractures, corresponding to $+45^\circ$0 yield over $+45^\circ$1 junctions (Skinner-Ramos et al., 1 Feb 2025). Since the method uses the same basic PMMA/MMA process and requires only a mask redesign, the result identifies bridge mechanics as a solvable design-level bottleneck rather than an unavoidable limitation of the Dolan topology.

4. Uniformity, critical-current variation, and geometry-dependent disorder

Beyond outright bridge survival, the dominant systems problem for Dolan junctions is junction-to-junction variation in critical current. A model-based analysis of $+45^\circ$2 Dolan-bridge junctions treats the measured room-temperature resistance distribution as a direct statistical proxy for critical-current variation via the Ambegaokar–Baratoff relation

$+45^\circ$3

and, for small fluctuations,

$+45^\circ$4

(Kakuyanagi et al., 29 May 2026). To suppress long-range wafer-scale effects, that study also uses the semivariogram

$+45^\circ$5

so that nearest-neighbor statistics mainly reflect intrinsic process variation rather than slow chip-scale drifts (Kakuyanagi et al., 29 May 2026).

The central variance decomposition is

$+45^\circ$6

with

$+45^\circ$7

and

$+45^\circ$8

(Kakuyanagi et al., 29 May 2026). In the fitted dataset, the dominant modeled contributions are the geometry-independent term $+45^\circ$9 and the film-thickness-related term $60\ \mathrm{nm}$0, while the area- and edge-related terms were driven to zero by the constrained fit. The stated physical conclusion is that among the modeled sources, Al film-thickness fluctuations dominate the intrinsic junction-to-junction variation in the studied Dolan-bridge process (Kakuyanagi et al., 29 May 2026).

The thickness-related contribution depends strongly on evaporation angle through the geometric factor

$60\ \mathrm{nm}$1

For bilayers $60\ \mathrm{nm}$2,

$60\ \mathrm{nm}$3

which vanishes at $60\ \mathrm{nm}$4 (Kakuyanagi et al., 29 May 2026). The paper interprets this as a bilayer-specific cancellation: the increase in sidewall contribution from a thickness increment is exactly canceled by the decrease in top-surface contribution, making the effective junction area first-order insensitive to small Al thickness fluctuations. No such null angle exists for $60\ \mathrm{nm}$5 (Kakuyanagi et al., 29 May 2026).

The reported data support this geometric interpretation. For bilayer junctions of width $60\ \mathrm{nm}$6, the normalized RMS variation drops from $60\ \mathrm{nm}$7 at $60\ \mathrm{nm}$8 to $60\ \mathrm{nm}$9 at $-45^\circ$0, an overall reduction by a factor of $-45^\circ$1 (Kakuyanagi et al., 29 May 2026). Across a $-45^\circ$2 square region, bilayer junctions deposited at $-45^\circ$3 exhibit a relative standard deviation of $-45^\circ$4 from $-45^\circ$5 valid samples, with mean resistance $-45^\circ$6 and standard deviation $-45^\circ$7; over smaller regions the spread falls to $-45^\circ$8 for $-45^\circ$9 square, $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$0 for $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$1 square, and $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$2 for $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$3 square (Kakuyanagi et al., 29 May 2026). This indicates that remaining chip-scale nonuniformity is dominated by long-correlation-length resist-thickness undulations from spin coating rather than by intrinsic short-range junction-fabrication noise.

5. Wafer-scale reproducibility and process-compensation strategies

Wafer-scale reproducibility studies treat Dolan junctions as a manufacturing problem in which both effective area and barrier thickness must be stabilized. One such process combines Shadow Evaporation Bias Correction and oxidation optimization for 4-inch wafers (Moskaleva et al., 2024). The model accounts for top and bottom resist thickness, substrate-holder tilt angle, crucible-to-substrate-holder distance, wafer position, actual angle variation over the wafer, finite evaporation source geometry, and sidewall deposition during the first evaporation step (Moskaleva et al., 2024). The practical output is a wafer map of bias corrections for resist-mask dimensions so that the deposited junctions land at the target area despite spatially varying shadow geometry.

The paper defines the area and resistance variation coefficients as

$$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$4

and states a square-root dependence linking qubit frequency and room-temperature resistance, written as $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$5 (Moskaleva et al., 2024). Over a $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$6 working area on 4-inch wafers, SEBi correction improves the junction area variation coefficient down to $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$7 for both $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$8 and $$E_J = \frac{\hbar I_c}{2e}, \qquad E_c = \frac{e^2}{2C_\Sigma},$$9 junctions, from about $I_c = \frac{\pi \Delta}{2eR_n},$0 and $I_c = \frac{\pi \Delta}{2eR_n},$1, respectively, before correction (Moskaleva et al., 2024).

The same study separates geometry-driven and barrier-driven contributions to room-temperature resistance spread. For a $I_c = \frac{\pi \Delta}{2eR_n},$2 working area with static oxidation and no SEBi, $I_c = \frac{\pi \Delta}{2eR_n},$3 is $I_c = \frac{\pi \Delta}{2eR_n},$4 for $I_c = \frac{\pi \Delta}{2eR_n},$5 $I_c = \frac{\pi \Delta}{2eR_n},$6 and $I_c = \frac{\pi \Delta}{2eR_n},$7 for $I_c = \frac{\pi \Delta}{2eR_n},$8 $I_c = \frac{\pi \Delta}{2eR_n},$9 (Moskaleva et al., 2024). With SEBi correction only, still using static oxidation, these reduce to $\mathrm{Al/AlO_x/Al}$00 and $\mathrm{Al/AlO_x/Al}$01, showing that about half the resistance variation came from area and geometry variation (Moskaleva et al., 2024). With SEBi plus optimized dynamic oxidation, the best reported values are $\mathrm{Al/AlO_x/Al}$02 and $\mathrm{Al/AlO_x/Al}$03 over $\mathrm{Al/AlO_x/Al}$04, $\mathrm{Al/AlO_x/Al}$05 and $\mathrm{Al/AlO_x/Al}$06 over $\mathrm{Al/AlO_x/Al}$07, and $\mathrm{Al/AlO_x/Al}$08 and $\mathrm{Al/AlO_x/Al}$09 over $\mathrm{Al/AlO_x/Al}$10 for $\mathrm{Al/AlO_x/Al}$11 junctions, respectively (Moskaleva et al., 2024).

The oxidation comparison is explicit. Static oxidation is reported as $\mathrm{Al/AlO_x/Al}$12 at $\mathrm{Al/AlO_x/Al}$13, whereas dynamic oxidation is explored at $\mathrm{Al/AlO_x/Al}$14 and either $\mathrm{Al/AlO_x/Al}$15 or $\mathrm{Al/AlO_x/Al}$16 (Moskaleva et al., 2024). The physical explanation given is that $\mathrm{Al/AlO_x/Al}$17 growth has a rapid initial stage up to roughly $\mathrm{Al/AlO_x/Al}$18 followed by slower growth, so low-pressure dynamic oxidation reduces the influence of oxygen intake and local concentration gradients, yielding more uniform tunnel barriers (Moskaleva et al., 2024). This suggests that, at wafer scale, Dolan-junction variability is best viewed as the superposition of a correctable geometric field and a tunable oxidation field.

6. Planar versus nonplanar integration, and comparison with Manhattan-style junctions

Comparative wafer studies show that the suitability of Dolan junctions depends strongly on substrate architecture. On fully planar substrates, Dolan junctions fabricated by double-angle shadow evaporation exhibit the highest yield and the lowest room-temperature conductance spread among the compared topologies (Muthusubramanian et al., 2023). On the planar 17Q wafer, the reported wafer-scale conductance coefficient of variation for Dolan junctions is $\mathrm{Al/AlO_x/Al}$19, the die-level predicted transmon-frequency residual standard deviation is around $\mathrm{Al/AlO_x/Al}$20, and the yield is $\mathrm{Al/AlO_x/Al}$21 (Muthusubramanian et al., 2023). Under the same planar conditions, bridgeless Manhattan junctions show conductance CV $\mathrm{Al/AlO_x/Al}$22 and yield $\mathrm{Al/AlO_x/Al}$23 (Muthusubramanian et al., 2023).

The situation reverses on TSV-integrated substrates. There, the spin-coated resist becomes less uniform because of TSV topography, and the paper argues that Dolan’s built-in sensitivity to resist-height variations becomes a liability (Muthusubramanian et al., 2023). On TSV wafers, Dolan junctions have $\mathrm{Al/AlO_x/Al}$24 yield with conductance CV $\mathrm{Al/AlO_x/Al}$25 and wafer-scale frequency RSD $\mathrm{Al/AlO_x/Al}$26 when the regression filter is applied (Muthusubramanian et al., 2023). TSV Manhattan junctions are comparatively better, with $\mathrm{Al/AlO_x/Al}$27 yield and conductance CV $\mathrm{Al/AlO_x/Al}$28, although still far from ideal (Muthusubramanian et al., 2023).

The contrast is instructive because it distinguishes two different failure modes. For Dolan junctions on planar wafers, the dominant issues are bridge mechanics, thickness-induced effective-area variation, and oxidation uniformity. For Dolan junctions on TSV-integrated wafers, resist-profile nonuniformity itself degrades the suspended-bridge process (Muthusubramanian et al., 2023). By contrast, Manhattan junctions exhibit a pronounced center-to-edge conductance decrease interpreted as geometric shadowing during evaporation, which can be modeled and partially corrected via actual overlap-area analysis from SEM images (Muthusubramanian et al., 2023). A common misconception is therefore that Dolan junctions are universally inferior to bridge-free alternatives; the comparative data support a more conditional statement: Dolan junctions are superior on planar wafers in the reported process flow, but Manhattan junctions are preferable on TSV wafers (Muthusubramanian et al., 2023).

7. Qubit performance, large-area implementations, and scope of the term

Dolan junctions are often associated with nanometric e-beam-defined transmon junctions, but the optical direct-write study shows that much larger lithographic areas can still produce coherent transmons when oxidation and surface preparation are carefully controlled (Monroe et al., 2021). In that work, a typical patterned bridge is $\mathrm{Al/AlO_x/Al}$29 long and $\mathrm{Al/AlO_x/Al}$30 wide, SEM imaging shows a typical Josephson junction lithographic area of about $\mathrm{Al/AlO_x/Al}$31, and the authors note that this is about two orders of magnitude larger than typical e-beam-defined qubit junctions $\mathrm{Al/AlO_x/Al}$32 (Monroe et al., 2021). The transmon devices use two large-area junctions in a SQUID geometry with a shunt capacitor of about $\mathrm{Al/AlO_x/Al}$33, are mounted in a copper cavity, cooled to $\mathrm{Al/AlO_x/Al}$34, and operated in the regime $\mathrm{Al/AlO_x/Al}$35 (Monroe et al., 2021).

The coherence metrics reported in that study include $\mathrm{Al/AlO_x/Al}$36, with tabulated values of $\mathrm{Al/AlO_x/Al}$37, $\mathrm{Al/AlO_x/Al}$38, and $\mathrm{Al/AlO_x/Al}$39, as well as $\mathrm{Al/AlO_x/Al}$40 and $\mathrm{Al/AlO_x/Al}$41 for select devices (Monroe et al., 2021). The paper attributes the improvement strongly to surface treatment: the best devices use a $\mathrm{Al/AlO_x/Al}$42 Piranha etch at $\mathrm{Al/AlO_x/Al}$43, followed by $\mathrm{Al/AlO_x/Al}$44 BOE before resist application, then oxygen plasma ashing for $\mathrm{Al/AlO_x/Al}$45 at $\mathrm{Al/AlO_x/Al}$46 with $\mathrm{Al/AlO_x/Al}$47 at $\mathrm{Al/AlO_x/Al}$48, then $\mathrm{Al/AlO_x/Al}$49 BOE before rapid transfer to UHV, with a base pressure around $\mathrm{Al/AlO_x/Al}$50 and about $\mathrm{Al/AlO_x/Al}$51 under vacuum to desorb contaminants (Monroe et al., 2021). The authors report nearly a five-fold increase in coherence time when multiple cleaning steps are used compared with no cleaning, and TLS observations are correspondingly reduced on average (Monroe et al., 2021).

Within the present literature, “Dolan junctions” should therefore be understood as a fabrication family rather than a single fixed geometry. It includes the classic e-beam-defined suspended-bridge $\mathrm{Al/AlO_x/Al}$52 qubit junction, process-modified versions with stress-relief channels, wafer-compensated variants with shadow-evaporation bias correction, and optical direct-write Dolan–Niemeyer-Bridge implementations (Skinner-Ramos et al., 1 Feb 2025). The common denominator is the use of a suspended resist bridge to define a self-aligned overlap during angled evaporation. A plausible implication is that the long-term scalability of this family depends less on abandoning the Dolan concept outright than on controlling bridge mechanics, local film-thickness fluctuations, oxidation transport, and substrate-induced resist nonuniformity at the process level.