Geometric dependence of critical-current variation in Al/AlO${\rm _x}$/Al Josephson junctions: a model-based analysis

Abstract: Achieving uniform critical current across Josephson junctions is essential for the large-scale integration of superconducting quantum circuits. In this work, we statistically analyzed the variation of the critical current of Al/AlO${\rm _x}$/Al junctions using room-temperature tunnel resistance statistics, and identified the dominant contribution among the modeled sources of the variation based on their dependence on geometry and deposition conditions of junctions. Our model-based analysis reveals that fluctuations in the Al film thickness play the dominant role among the modeled contributing factors. Based on this analysis, we found that, in Dolan-bridge double-angle deposition, adopting a deposition angle of 30-degree for bilayer junctions significantly improves uniformity, yielding a relative standard deviation of 1.2% (0.5%) across a 9.75 mm (1.5 mm) square region.

• The paper introduces a statistical model that isolates geometry-independent noise and film-thickness fluctuations as key contributors to critical-current variation.
• Experimental results on ~4000 junctions show that a 30° bilayer deposition minimizes film-thickness-induced variability, achieving sub-percent RMS resistance variation.
• The findings provide actionable design rules by linking deposition parameters to uniformity, enabling scalable quantum circuit fabrication with reduced calibration overhead.

Model-Based Analysis of Critical-Current Variation in Al/AlO${\rm _x}$/Al Josephson Junctions

Motivation and Background

Uniformity in the critical current ($I_\mathrm{C}$) of Josephson junctions is paramount for large-scale superconducting quantum circuit integration, as device-to-device variation directly impacts qubit frequency allocation, circuit performance, and reliability. Al/AlO$_x$/Al Josephson junctions fabricated by the Dolan-bridge technique remain foundational in this technological landscape, yet the microscopic origins of $I_\mathrm{C}$ variations have not been fully elucidated, restricting progress toward wafer-scale integration with minimal calibration requirements.

Recent literature reports have demonstrated (few)-percent-level critical-current uniformity over large areas through lithography and process optimizations, but a detailed quantitative understanding of the process-induced variation routes, spatial scales, and mitigation strategies is lacking. This paper presents a comprehensive statistical and model-based analysis targeting these open questions.

Statistical Model and Methodology

The authors construct a model for fluctuations in critical current by decomposing the normal-state conductance variation ($\delta G_N$) as the sum of independent stochastic components, corresponding to geometry-independent processes, junction-area scaling, edge roughness, and film-thickness fluctuations. The model explicitly incorporates dependencies on junction width, area, perimeter, number of deposition layers ($N_\mathrm{L}$), and deposition angle ($\theta$). The contributions are parameterized as follows:

• Geometry-independent term ($c_0$): Attributable to spatially invariant process noise.
• Area and perimeter terms ($c_S, c_{S^2}, c_L, c_{L^2}$): Reflecting random microscopic fluctuations in oxide barrier thickness, edge patterning, and resist thickness gradients.
• Film-thickness-related term ($c_d f^2(\theta, N_\mathrm{L})W^2$): Quantifying sensitivity to local Al film thickness fluctuations via a geometric factor derived from the Dolan-bridge shadow-evaporation process.

The semivariogram formalism is employed to extract the intrinsic, short-range process-induced variation by suppressing long-range spatial artifacts and wafer-scale gradients. Measurements of room-temperature tunnel resistance serve as the primary observable, mapped to critical current via the Ambegaokar–Baratoff relation.

Experimental Investigation and Quantitative Results

The study involves the fabrication of $I_\mathrm{C}$04000 junctions with systematically varied geometries across Si chips, using Dolan-bridge shadow evaporation at $I_\mathrm{C}$117° and $I_\mathrm{C}$230° deposition angles, and implementing both bilayer ($I_\mathrm{C}$3) and trilayer ($I_\mathrm{C}$4) schemes.

Key Quantitative Findings:

• For bilayer junctions at 17°, the model decomposes the normalized RMS resistance variation as $I_\mathrm{C}$5 film-thickness-related and $I_\mathrm{C}$6 geometry-independent, with other contributions negligible within fitting uncertainty.
• Trilayer junctions exhibit substantially reduced film-thickness-related variance, consistent with statistical averaging over independent deposition events.
• Increasing the junction width effectively suppresses relative geometry-independent variation, confirming practical fabrication insights.
• At 30° deposition, the normalized RMS variation for bilayer devices is measured at $I_\mathrm{C}$7, representing a reduction by a factor of 1.67 compared to 17°, which exceeds the reduction predicted by area scaling alone, in strong agreement with the vanishing geometric factor for film-thickness sensitivity at 30° for bilayers.
• In optimized conditions (bilayer, 30°, $I_\mathrm{C}$8), the global relative standard deviation of resistance is $I_\mathrm{C}$9 (over a $_x$0 chip area). In defect- and artifact-free $_x$1 regions, the minimum value achieved is $_x$2 for 121 samples—satisfying the most stringent device-uniformity requirements in current quantum processor designs.

Implications and Theoretical Insights

The analysis unambiguously identifies local Al film-thickness fluctuations, modulated by the shadow-evaporation geometry, as the dominant source of critical-current variance in these Josephson junctions. The mathematical formalism provides closed-form design rules governing deposition angle and multilayer geometry, facilitating reproducible suppression of $_x$3 variation without reliance on process trial-and-error.

The vanishing of the film-thickness-induced contribution at a bilayer deposition angle of 30° emerges directly from the geometric factor, a result that sharply differentiates this source of variation from other process noise. This not only offers a direct mitigation route but also supports diagnostic discrimination between competing sources of nonuniformity in experimental process characterization.

Spatial analysis reveals that resist-thickness undulations introduced in spin-coating dominate long-range spatial deviations, but local (intrinsic) process-induced variation sets the achievable lower bound. The results confirm that, with further improvements in resist-coating uniformity, sub-0.5% $_x$4 variation is attainable, thus significantly reducing calibration overhead in frequency allocation for multi-qubit platforms.

Impact on Future Quantum Hardware Development

This model-based framework generalizes to other junction geometries, process recipes, and scale-up strategies. The statistical decomposition is compatible with alternative superconducting materials and can guide process optimization in contexts such as large-scale JTWPA arrays or hybrid superconductor-semiconductor circuits. By sharply quantifying each source of variation and linking mitigation to clear geometric parameters, the work provides actionable guidelines for next-generation wafer-scale quantum hardware fabrication.

Future research directions include:

• Integration of more complex deposition and oxidation models.
• Application of the model to advanced junction types (e.g., cross-type or submicron in-plane geometries).
• Systematic exploration of wafer-scale patterning and resist-coating optimization to push uniformity below current device-limited levels.

Conclusion

This work rigorously demonstrates, via statistical modeling and experimental validation, that local Al film-thickness fluctuations—dictated by precise geometric and deposition parameters—set the dominant limit for critical-current uniformity in Al/AlO$_x$5/Al Josephson junctions fabricated with the Dolan-bridge process. The identification of a null in the thickness-induced variation at a 30° bilayer evaporation angle provides a practically accessible, geometry-driven route to sub-percent-level uniformity. These insights supply both immediate process-design guidance for scalable quantum hardware and a general statistical framework for the analysis of process-induced device variability in superconducting circuits.