Digital Mixing and Down-Sampling (DMD)

• DMD is a technique that couples digital mixing with down-sampling to translate and decimate signals in modern receivers.
• Implementations vary: one form uses a DDS/NCO-based mixer in PLCC ASIC, while another utilizes a parallel PFB/FFT channelizer in the YTLA system.
• Calibration and equalization are critical in DMD to achieve effective image suppression and high sideband rejection ratios.

Searching arXiv for the papers on arXiv and closely related DMD/DDC work to ground the article in cited sources. Digital Mixing and Down-Sampling (DMD) denotes the pair of operations “Digital Mixing + Down-Sampling.” Mixing multiplies a digitized bandpass signal by a locally generated sinusoid so that the desired channel moves to baseband; down-sampling then reduces the sampling rate after sufficient anti-alias filtering confines the signal to the new Nyquist region. In the Yuan‑Tseh Lee Array (YTLA), DMD is realized in a digital sideband‑separating down‑conversion receiver that digitizes quadrature baseband at 5 GS/s and uses a polyphase filter bank (PFB) followed by a 1024‑point FFT and per‑channel complex recombination to deliver two simultaneous 1.6 GHz sidebands within a tunable 3.2 GHz window of a 2–18 GHz IF, with sideband rejection ratios (SRRs) above 20 dB after equalization and above 30 dB after calibration (Li et al., 2022). In a PLCC digital down converter (DDC), DMD is the receive‑side counterpart of digital up conversion (DUC): a DDS/NCO-driven mixer translates a 200–500 kHz carrier to baseband, and a decimation chain dominated by a 5-stage CIC reduces 1.28 MHz sampling to 64 kHz for 300–4000 Hz audio (Bhat, 2012).

1. Definition, scope, and system roles

DMD is a receive-side operation in which frequency translation and sample-rate reduction are coupled. In the PLCC receiver, the ADC produces a 14-bit stream at 1.28 MHz containing audio (300–4000 Hz) amplitude-modulated on a 200–500 kHz carrier; the DDC mixes the stream with a tunable DDS tone, low-pass filters the mixer output, and decimates by 20 to reach 64 kHz. In the YTLA receiver, the implementation is wider-band and multichannel: the analog front end produces an IF from 2 to 18 GHz, analog I/Q generation converts a selected window to baseband, two 5 GS/s ADCs digitize the I and Q streams, and FPGA-resident channelization and recombination produce upper and lower sidebands, each spanning 1.6 GHz (Li et al., 2022).

The two realizations illustrate two distinct but compatible interpretations of DMD. In the PLCC ASIC, DMD appears in its canonical single-channel DDC form: DDS/NCO mixing followed by decimation. In the YTLA receiver, the same functional triad—mixing, anti-alias filtering, and down-sampling—is distributed across a critically sampled PFB/FFT channelizer, with explicit scalar NCO mixing replaced by FFT basis functions and per-channel recombination. This suggests that DMD is best understood as an architectural pattern rather than a single block-level topology.

Aspect	YTLA	PLCC ASIC
Input regime	IF 2–18 GHz, quadrature baseband digitized at 5 GS/s	14-bit ADC at 1.28 MHz
Mixing realization	FFT acts as a parallel bank of complex oscillators; analog LO positions the window	DDS/NCO-generated LO at 200–500 kHz
Rate reduction	Critically sampled PFB/FFT channelizer	5-stage CIC decimator by 20 with compensation FIR

2. Signal model and mathematical formulation

For analog I/Q down-conversion in the YTLA chain, with an LO chosen near the center of the desired IF window, the ideal baseband relations are

$$I(t)=s(t)\cos(2\pi f_{LO} t), \qquad Q(t)=s(t)\sin(2\pi f_{LO} t),$$

where $s(t)$ is the IF signal in the mixer RF port after IF splitting. Sampled at $f_s = 5$ GS/s,

$I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$

Complex baseband is then

$x[n]=I[n]+jQ[n].$

In a general DMD framework, one can shift a selected window by

$x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$

In the YTLA implementation, the analog LO positions the 3.2 GHz window and the FFT itself acts as a parallel bank of complex oscillators, so explicit scalar NCO mixing is not required for coarse tuning (Li et al., 2022).

In the PLCC DDC, if $x[n]$ is the received bandpass sequence at $F_s$, mixing by a complex LO gives

$s[n]=x[n]\cdot e^{-j2\pi f_{LO} n/F_s}.$

For real-valued implementations it is common to form

$$s_I[n]=x[n]\cos(2\pi f_{LO} n/F_s), \qquad s_Q[n]=-x[n]\sin(2\pi f_{LO} n/F_s).$$

With $s(t)$0 near the carrier center, the difference term contains the baseband audio and the sum term is far from DC. After low-pass filtering, decimation by $s(t)$1 is

$s(t)$2

The anti-alias condition is stated as

$s(t)$3

so that energy outside the new Nyquist region does not fold into baseband (Bhat, 2012).

The YTLA sideband-separating stage introduces an additional frequency-domain recombination. Under ideal balance,

$s(t)$4

With amplitude and phase imbalance, the I and Q paths are modeled by complex gains $s(t)$5 and $s(t)$6, then equalized by per-bin weights $s(t)$7 and $s(t)$8 before recombination. In the implemented calibration, $s(t)$9 and $f_s = 5$0, $f_s = 5$1 are derived from per-bin amplitude ratios and phase differences measured from test tones, following Morgan and Fisher (Li et al., 2022).

3. Wideband multichannel DMD in the Yuan‑Tseh Lee Array

The YTLA implementation begins with a MMIC HEMT LNA front end at 3 mm wavelength feeding a W-band receiver front end. The receiver is intrinsically single-sideband at RF with a high-pass filter in front of sub-harmonic mixers, which produce IF from 2 to 18 GHz. A broadband 90° LO hybrid with $f_s = 5$2 dB amplitude imbalance and $f_s = 5$3 phase imbalance from 1–18 GHz delivers in-phase and quadrature LO drives to two balanced mixers. The IF is split by a 1.5–18 GHz power divider and fed to both mixers, which down-convert to baseband $f_s = 5$4 and $f_s = 5$5. Baseband conditioning then uses 30 dB gain amplifiers (2.5 MHz–2.5 GHz), variable attenuators for power balance, 10 dB directional couplers for monitoring, and analog low-pass anti-alias filters prior to ADCs (Li et al., 2022).

Digitization uses two 5 GS/s, 8-bit ADC boards, one per baseband stream. Each device interleaves four 1.25 GS/s cores to achieve 5 GS/s in “one-channel” mode. The FPGA platform is CASPER ROACH2 with a Virtex-6 FPGA. ADC data are received over Z-Dok; Xilinx ISERDES is used to demultiplex incoming high-rate serial data. The ADC provides demux by 4, ISERDES adds demux by 4, and an additional demux by 2 yields a 125 MHz system clock instead of 250 MHz for 2 GHz/sideband operation. This reduction in fabric clock is explicitly used to ease timing for large designs.

The channelizer is a PFB followed by a 1024-point FFT. In the stated formulation, the PFB/FFT converts time-domain samples to frequency channels with flattened channel responses and suppressed leakage; this realizes the DMD functionality in a multichannel fashion and provides the second IF hybrid digitally via per-channel complex recombination. The block-diagram description is RF (W-band) $f_s = 5$6 sub-harmonic mixers $f_s = 5$7 IF 2–18 GHz $f_s = 5$8 analog 90° LO hybrid + two mixers $f_s = 5$9 baseband $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$0 (0–2.5 GHz after analog LPF) $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$1 5 GS/s ADCs $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$2 FPGA demux/ISERDES $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$3 PFB $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$4 FFT (1024 channels) $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$5 per-channel digital mixing implicit in FFT bins $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$6 per-channel anti-leakage via PFB $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$7 per-channel decimation implicit in critically sampled PFB/FFT $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$8 digital second hybrid using $I[n]=I(n/f_s), \qquad Q[n]=Q(n/f_s).$9 $x[n]=I[n]+jQ[n].$0 USB and LSB spectra, each spanning 1.6 GHz (Li et al., 2022).

The tunability is hybrid analog-digital. The analog LO frequency positions the $x[n]=I[n]+jQ[n].$1 GHz digital outputs within the 2–18 GHz IF. Each sideband is channelized into 1024 bins, giving $x[n]=I[n]+jQ[n].$2 GHz / 1024 $x[n]=I[n]+jQ[n].$3 MHz per bin. The combined tunable window is 3.2 GHz. A plausible implication is that the YTLA architecture uses analog frequency placement for coarse selection and frequency-domain coefficient control for fine balancing and sideband purification.

4. DDS/CIC DMD in the PLCC ASIC

The PLCC ASIC DDC implements DMD in a more conventional receive chain. ADC input and output registers are synchronized to derived 1.28 MHz and 64 kHz clocks, respectively. A programmable DDS/NCO generates a sinusoid at $x[n]=I[n]+jQ[n].$4 in 200–500 kHz at the same 1.28 MHz sampling rate. In RTL, a phase accumulator and 256-entry sine LUT with 8-bit samples implement the LO, and the frequency control word determines phase step size. The mixer multiplies the 14-bit input stream by the LO samples; in theory and best practice, complex I/Q mixing suppresses the image, while the RTL shows a real-valued multiply with downstream filtering selecting the desired component. Product width grows to $x[n]=I[n]+jQ[n].$5 in the waveforms shown (Bhat, 2012).

The anti-alias and decimation chain is dominated by a 5-stage Hogenauer CIC doing decimate-by-20. The integrator section runs at 1.28 MHz and the comb section runs at 64 kHz. Internal buses are wide, for example $x[n]=I[n]+jQ[n].$6, to accommodate CIC gain. The compensation FIR is MAC-based and removes CIC passband droop. In the MATLAB model, this “compensation & decimate-by-2” filter implements a further factor-of-2 decimation, giving a 10× CIC followed by 2× FIR for 20× total; in the ASIC, the CIC alone performs 20× decimation and the compensation FIR is kept as a straight-through low-pass equalizer.

The CIC response is given as

$x[n]=I[n]+jQ[n].$7

For the implemented case, $x[n]=I[n]+jQ[n].$8, $x[n]=I[n]+jQ[n].$9, and $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$0. The passband droop within 0–4 kHz is corrected by the compensation FIR. The role of the DMD chain is therefore explicit: translate a tunable carrier to baseband, reject the high-frequency image and out-of-band components, and reduce the rate from 1.28 MHz to 64 kHz while preserving the 300–4000 Hz audio band.

The ASIC realization is described at system level with technology and implementation detail. It uses TSMC 65 nm, a 64 MHz master clock, derived 1.28 MHz and 64 kHz clocks, and a Multi-VDD low-power architecture. DDC power is reduced from 176.26 μW (1.08 V) to 124.47 μW (0.9 V + 1.08 V domains), while DUC power is reduced from 280.9 μW to 198.07 μW. The DDC die area after budgeting is approximately 48,506.8 μm$x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$1 with start utilization 70%; routing achieved zero DRC/LVS violations, timing met in worst and best corners, and gate-level and post-route simulations were clean (Bhat, 2012).

5. Calibration, equalization, and rejection performance

In the YTLA receiver, calibration is central to practical DMD because the digital second hybrid is only as effective as the balance between I and Q. Power equalization is performed with analog variable attenuators assisted by 10 dB directional couplers. FPGA delay blocks remove phase wraps seen in $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$2 cross-correlations and equalize group delay between the I and Q paths; measured delay ripple is influenced by standing waves between the analog module and ADCs. Per-bin coefficient calibration is then performed by injecting a test tone, measuring per-bin $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$3 cross-spectra for USB and LSB after PFB/FFT, computing amplitude ratios $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$4, $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$5 and phases $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$6, $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$7, and deriving $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$8 and $x_{\mathrm{mix}}[n]=x[n]e^{-j2\pi f_0 n/f_s}.$9 with $x[n]$0 (Li et al., 2022).

The measured outcomes are stated directly. Before calibration, with band-limited noise and nominal coefficients, SRR $x[n]$1 dB across the 3.2 GHz window is obtained after power and delay adjustments; CW tests show image signals in the opposite sideband and ADC-related spurs. After calibration, applying $x[n]$2 derived from per-bin measurements suppresses images further, and SRR exceeds 30 dB across both 1.6 GHz sidebands. Standing waves cause SRR ripple with approximately 50 MHz period, corresponding to an approximately 2.1 m coax round-trip. Large coefficient variations occur near analog filter cutoffs because of rapid amplitude and group-delay changes; the use of flatter, linear-phase filters is noted as helpful.

The standard image-rejection relation is also given:

$x[n]$3

where $x[n]$4 and $x[n]$5 is the phase error between I and Q. For small errors, with $x[n]$6 and $x[n]$7,

$x[n]$8

These relations are not explicitly stated in the paper but are described as consistent with the observed need to equalize amplitude and correct delay or phase to achieve SRR above 20–30 dB (Li et al., 2022).

In the PLCC ASIC, the dominant calibration concerns are different. The paper focuses on functional, timing, and power validation rather than reporting SNR, SFDR, THD, or exact filter attenuation and ripple numbers. Nevertheless, several implementation-sensitive limits are identified: real-valued mixing leaves an image; DDS LUT size and phase width constrain SFDR; CIC passband droop requires compensation; and internal word lengths must accommodate worst-case Hogenauer gain. In this setting, DMD performance is bounded less by sideband rejection than by quantization, spur management, and low-pass equalization (Bhat, 2012).

6. Architectural trade-offs, misconceptions, and design guidance

A recurrent misconception is that DMD necessarily implies an explicit numerically controlled oscillator followed by a decimator. The PLCC ASIC conforms to that pattern, but the YTLA implementation shows a broader realization in which a critically sampled PFB/FFT provides, in parallel across channels, anti-leakage filtering, complex mixing to channel centers, and decimation to per-bin rates. The underlying operation is still DMD; the architecture is simply channelized rather than scalar (Li et al., 2022).

A second misconception concerns the relation between DMD and sideband separation. DMD itself is frequency translation plus sample-rate reduction. In the YTLA receiver, sideband separation is performed by a digital second hybrid after channelization, using calibrated complex coefficients $x[n]$9. Thus the sideband-separating function is built on top of DMD rather than replacing it. Conversely, in the PLCC ASIC, the emphasis is on recovering a low-rate baseband signal from a bandpass input, without an analogous USB/LSB split.

The papers also document architecture-specific ambiguities. In the PLCC DDC description, a high-pass filter following the mixer is said to “select the upper band (carrier + signal frequency).” The same source notes that the standard DDC path is mix to baseband, low-pass, then decimate, and that the CIC plus compensation FIR together provide the anti-alias low-pass needed for decimation to 64 kHz. The HPF mention is therefore described as an implementation artifact or a mode used elsewhere in the chain rather than the core receive-side selection mechanism (Bhat, 2012).

The design guidance stated across the two implementations is consistent. Low-jitter clocks are required; tight interleaving calibration minimizes ADC spurs; power and delay equalization should precede per-bin or per-stage coefficient calibration; matched impedance, proper terminations, and minimized cable lengths reduce standing waves; flatter amplitude and linear-phase analog anti-alias filters reduce calibration density near cutoffs; and precise I/Q alignment remains fundamental. In the PLCC case, additional guidance includes budgeting internal bit growth as input bits plus $F_s$0 plus headroom, using CIC for bulk decimation and FIR compensation for droop correction, and considering DDS phase dithering, larger LUTs, and quadrature generation when higher SFDR or image rejection is required (Bhat, 2012).

Taken together, these realizations establish DMD as a general digital receiver primitive. In one form it is a low-power ASIC chain for translating a 200–500 kHz carrier to a 64 kHz audio stream. In another it is a wideband radio astronomy backend in which high-rate quadrature digitization, PFB/FFT channelization, and calibrated digital recombination deliver two simultaneous 1.6 GHz sidebands from a tunable 3.2 GHz IF window. The common structure is invariant: controlled digital frequency translation, anti-alias suppression, and rate reduction matched to the bandwidth of the retained information.