CACTUS: CSNR-Optimal ADC for AIMC

• CACTUS is a CSNR-optimal ADC architecture that maximizes dot-product accuracy in AIMC by aligning ADC parameters with analog in-memory computing characteristics.
• It employs a closed-form optimization and iterative search to set quantizer thresholds and step-sizes, significantly reducing energy consumption and ADC precision requirements.
• The design achieves order-of-magnitude energy savings and improved signal fidelity, enabling a 3-bit reduction in ADC resolution while meeting high CSNR targets.

A Compute SNR-optimal ADC, referred to as "CACTUS" (Compute Accurate Conversion via Threshold and Uniform Step search, Editor's term), is an analog-to-digital converter (ADC) framework and architecture jointly developed at the interface of analog in-memory computing (AIMC) and digital signal quantization. CACTUS is designed specifically to maximize the compute signal-to-noise ratio (CSNR) in AIMC tasks—most notably analog SRAM-based dot-product accelerators—powering high-precision deep neural inference with significant reductions in column ADC energy overhead. Unlike traditional methods that maximize signal-to-quantization-noise ratio (SQNR) under generic noise models, CACTUS explicitly targets the preservation of the dot-product accuracy intrinsic to computing in memory, enabling order-of-magnitude efficiency improvements at iso-accuracy (Yoshioka, 2023, Kavishwar et al., 13 Jul 2025).

1. AIMC Dot-Product Model and Definition of CSNR

Within the analog in-memory computing paradigm, column-parallel dot products are realized by accumulating charge on a bitcell array according to binary input and weight vectors ($\mathbf{x}, \mathbf{w} \in \{0,1\}^N$). The ideal digital dot product $y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$ generates discrete analog levels after scaling ($V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$), which are then subject to analog noise ($\eta_a \sim \mathcal{N}(0, \sigma_a^2)$), producing the pre-ADC signal $V_{\rm pre}$.

The column ADC performs a quantization operation, and its digital output is mapped back to a representation of the original dot product. The core metric for evaluating the ADC's impact on computational fidelity is the compute SNR (CSNR): $$\mathrm{CSNR} = \frac{\mathrm{Var}(y_{\rm ideal})} {\mathbb{E}[(y_{\rm imc}-y_{\rm ideal})^2]}$$ where $y_{\rm imc}$ is the quantized and decoded output. This definition fundamentally contrasts with the traditional SQNR, which does not account for the discrete nature of $y_{\rm ideal}$ or the AIMC context (Kavishwar et al., 13 Jul 2025).

2. The CACTUS Optimization Algorithm

CACTUS is a targeted quantizer-parameter search methodology that maximizes CSNR by identifying the ADC parameters—thresholds and step-sizes—that directly minimize mean-squared dot-product error. Key insights include:

• Lock-In Principle: CSNR exhibits sharp, non-convex peaks as a function of quantizer boundaries, aligning whenever the ADC quantization step size ($\Delta_{\rm adc}$) is an integer multiple of the dot-product level spacing ($\Delta_{\rm imc}$), and thresholds are centered between discrete analog levels.
• Closed-Form CSNR: Leveraging the exact mixture distribution of $y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$0 and the PMF $y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$1 of the dot product, CACTUS uses analytical solutions (Theorems 1 and 2, (Kavishwar et al., 13 Jul 2025)) to compute calibration offsets, MSE, and maximal CSNR for a given bit-width.

The core algorithm iteratively searches over candidate quantizer step-sizes and positions, selecting the configuration yielding minimal error. CACTUS can be further inverted to find the minimum ADC precision ($y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$2) required to achieve a target CSNR.

Summary Table: CACTUS Search Parameters

Parameter	Role	Comments
$y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$3	Dot-product step (analog scale)	Fixed by array sizing, post-layout extraction
$y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$4	ADC resolution (bits)	Search range $y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$5
$y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$6	ADC thresholds	Constrained to "midpoints" between adjacent analog levels
$y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$7	Analog noise (standard dev.)	Technology- and design-dependent, e.g., 0.5–1 mV

3. CSNR-Optimal ADC Circuit Realizations: Dual-Use Capacitor-Reconfiguring Topology

Practical implementation of CACTUS-based CSNR-optimality is exemplified in the CR-CIM macro (Yoshioka, 2023), which unifies analog MAC and ADC functionalities within a shared array of precision-matched capacitors:

Compute Phase (MAC):

• Bitcell: 6T SRAM plus fringe capacitor ($y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$8, approx. 1.5 fF).
• Input: 10-bit thermometric drive loads weighted by SRAM content; charge accumulates directly on capacitors.

ADC Phase (SAR Conversion):

• Reuses the $y_{\rm ideal} = \mathbf{w}^T\mathbf{x}$9 array as a 10-bit binary C-DAC, with per-bit digital control ($V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$0) forming a $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$1-level binary ladder under a single comparator.
• No off-array charge redistribution; maximal signal swing ($V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$2 rather than $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$3), eliminating attenuation (attenuation factor $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$4 in conventional architectures).
• Result: $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$5 larger signal swing, $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$6 relaxed comparator noise requirement, yielding a $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$7 reduction in comparator energy for iso-CSNR.

4. Mathematical Impact on CSNR and Energy/Precision Trade-offs

The removal of off-array attenuation directly yields a CSNR improvement of approximately $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$8 dB, as: $V_{\rm ideal} = y_{\rm ideal} \Delta_{\rm imc}$9 By doubling the acceptable comparator input-referred noise at fixed CSNR, comparator energy reduces fourfold, since energy scales as the square of input noise.

System-level implications are underscored in (Kavishwar et al., 13 Jul 2025): for a 256-dimensional SRAM AIMC (with $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$0 mV, $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$1 mV), CACTUS enables a 3-bit reduction in ADC precision for a 30 dB CSNR target (6 bits CACTUS vs. 9 bits conventional). Since ADC energy scales as $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$2, this translates to $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$3 energy savings per column ADC and roughly $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$4 at the full chip level (assuming ADCs account for 60% of power).

5. Software-Analog Co-Design: Dynamic Majority Voting

CACTUS incorporates a software-analog co-design methodology to further optimize layer-specific inference requirements in transformer workloads:

• Attention layers: Typically require CSNR ≈ 25 dB; single-shot SAR mode suffices.
• MLP layers: Demand CSNR ≈ 31 dB; dynamic "CSNR-Boost" mode enabled.
• Majority Voting: During the last 3 SAR bits, each comparator decision is repeated six times; a majority rule resolves the output, lowering bit error rate (from $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$5 to $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$6), and boosting CSNR by $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$7 dB. Overheads are limited ($\eta_a \sim \mathcal{N}(0, \sigma_a^2)$8 power, $\eta_a \sim \mathcal{N}(0, \sigma_a^2)$9 time), and dynamically gated via FSM flag with no hardware changes.

6. Figures-of-Merit: SQNR/CSNR and Benchmarking Results

Performance is jointly evaluated via SQNR and CSNR-based figures-of-merit (FoM): $V_{\rm pre}$0 Measured for CACTUS (CR-CIM + CB): at 818 TOPS/W, SQNR = 45 dB ($V_{\rm pre}$1), CSNR = 31 dB ($V_{\rm pre}$2), representing respective $V_{\rm pre}$3 and $V_{\rm pre}$4 improvements over prior state-of-the-art charge-CIMs (Yoshioka, 2023).

7. Timing, Reconfiguration, and Operational Characteristics

The CACTUS-based CR-CIM macro employs a strictly phased operation:

• Compute: Input driving and charge accumulation.
• Reset (RST): Global switch to stabilize held charge.
• SAR bit trials (SA9–SA3): Standard single-comparator cycles.
• CSNR-Boost bits (SA2–SA0): Multiple compare/vote cycles when enabled.
• Ready: Output available post-cycle.

Dynamic mode switching (CB mode) ensures optimal energy allocation tuned to the workload's precision needs without sacrificing performance. The architecture keeps the MAC charge resident within the same capacitor array, maintaining high signal integrity and enabling maximal compute SNR benefit.

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In sum, CACTUS advances the state-of-the-art in ADC design for analog in-memory computing by unifying circuit-level capacitor reconfiguration, closed-form quantizer optimization, energy proportionality, and algorithm-hardware co-design. The result is demonstrable order-of-magnitude energy-efficiency improvements at fixed DNN accuracy, making CACTUS a reference approach for future AIMC systems seeking optimal trade-offs between precision, energy, and area (Yoshioka, 2023, Kavishwar et al., 13 Jul 2025).