Charge-Based ACIM: Principles & Applications

• Charge-Based ACIM is a methodology that leverages charge manipulation for analog computation, chemical modeling, and quantum sensing, enabling efficient dot-product operations.
• Key implementations include SRAM-based compute-in-memory circuits with MOM capacitors and AIM charge partitioning for robust molecular modeling.
• Optimized circuit designs achieve high energy efficiency, linearity up to 12 bits, and up to 4094 TOPS/W performance while effectively mitigating noise and leakage.

Charge-based ACIM refers to a set of methodologies that leverage charge as the physical variable for analog computation, measurement, or chemical modeling across disparate research domains. Significant implementations are found in analog compute-in-memory circuits for efficient matrix-vector multiplication in hardware accelerators; in electronic structure theory for atoms-in-molecules (AIM) charge partitioning; and in radio-frequency charge sensing for mesoscopic device readout. Each context defines distinct operational principles but shares the common concept of using charge distribution or manipulation as the information carrier.

1. Fundamental Operational Principles in Hardware Accelerators

In analog Compute-in-Memory (ACIM) architectures, charge-based approaches encode computation in the accumulation and redistribution of charge across a capacitor network. Specifically, digital weights are stored in standard 6T SRAM cells, which control the connection between bit-lines and local metal-oxide-metal (MOM) capacitors. Input voltages, representing activations, are applied to the bit-lines. The per-cell multiplication is realized by conditional charge transfer—effected by logic (e.g., XNOR, AND)—to the local MOM capacitor. Upon completion of the multiply phase, the charge on each MOM is summed along a column or row, encoding the result of an analog dot-product. High linearity and robustness to process-voltage-temperature (PVT) variations are achieved due to the physical properties of the MOM capacitor and digital switch-capacitor logic (Yoshioka et al., 2024).

2. Circuit Topologies and Switching Protocols

The multiplying bit cell (M-BC) is based on a conventional 6T SRAM topology, augmented with two p-MOSFET switches connecting the bit-lines to the MOM capacitor. The MOM capacitor is fabricated in the upper metal layers to avoid area penalty. The charge summing is executed along a shared node, typically column-wise, which then feeds a column-parallel successive approximation register analog-to-digital converter (SAR ADC) for digital conversion.

The operation is organized in four clocked phases:

• Reset: Pre-charge sum nodes and capacitors to a reference $V_{\rm ref}$.
• Weight-Set: Conditionally ground or retain the MOM capacitors based on SRAM state.
• Input-Multiply: Apply $V_{\rm IN}$ to bit-lines, causing charge redistribution.
• Read/Convert: ADC digitizes the final analog voltage $V_{\rm SUM}$ encoding the dot-product (Yoshioka et al., 2024).

3. Mathematical Description and Noise Models

The analog dot-product is computed as

$Q_{\rm total} = \sum_{i=1}^N C_i V_i$

where $C_i$ is the effective capacitance for cell $i$ (proportional to the stored weight), and $V_i$ is the applied input voltage. The resulting analog voltage is

$V_{\rm out} = \frac{\sum_i C_i V_i}{\sum_i C_i}$

for binary-weighted capacitor arrays. For digital weights and activations, a bit-serial or bit-parallel scheme reconstructs the multi-bit output. Noise and non-idealities, such as ADC quantization error and analog disturbances (thermal, mismatch, non-linearity), degrade the compute signal-to-noise ratio (CSNR), which is formally

$$\mathrm{CSNR} = 10\log_{10}\left(\frac{\mathbb{E}[y_{\rm D}^2]}{\mathbb{E}[(y_{\rm D} - y_{\rm A})^2]}\right)$$

(Yoshioka et al., 2024).

4. Performance, Area, Precision, and Comparison

Charge-based ACIM achieves high energy and area efficiency, exemplified by macro-scale throughputs up to 4094 TOPS/W (capacitor-reconfigured designs), and cell densities aligning closely with traditional SRAM+MOM configurations. SAR-ADC-based charge summation delivers linearity up to 12 bits, and MOM capacitors provide sub-0.1% PVT-induced capacitance variation. Primary noise sources are capacitor thermal noise and switch charge injection; with careful design, >20 dB CSNR is attained (sufficient for CNNs), and >30 dB for transformer networks with minimal accuracy loss. Table I in (Yoshioka et al., 2024) contrasts charge-based, current-based, and time-based ACIM, highlighting the high linearity and PVT resilience of charge-domain logic, albeit with increased ADC precision demands.

ACIM Type	Multiplication Principle	Key Strengths	Key Weaknesses
Charge-based	Switch-capacitor	High linearity, PVT	Requires high-precision ADC
Current-based	gm-cell drain current	Compact cell	Strong non-linearity, PVT
Time-based	Delay encoding	Ultra-small, digital	High PVT, non-linear delay

5. Design Constraints and Mitigation Techniques

Principal challenges include charge leakage and finite switch resistance (limiting dynamic range), device mismatch (offset), and dominant thermal $kT/C$ noise. Mitigations entail restricting accumulation windows, boosting gate drive, background ADC calibration, and redundancy in capacitor arrays. SAR ADC overhead is reduced in capacitor-reconfigured topologies by reusing bit cell capacitors for the ADC and incorporating input sparsity sensing to dynamically lower effective ADC resolution. Trade-offs between dynamic range and ADC resolution are handled via bit-parallel extensions and mixed-domain hybridizations wherein most significant bits (MSBs) are computed digitally (Yoshioka et al., 2024).

6. Integration with Digital CIM and System-Scale Architectures

Hybrid DCIM/ACIM schemes partition dot-products such that MSBs are handled by DCIM and LSBs by charge-based ACIM, delivering up to 2× energy savings at 8-bit precision with negligible accuracy loss. Saliency-aware dynamic hybrids route only high-importance columns to DCIM, using runtime saliency prediction for system-level energy reductions (20–40%) under tight accuracy constraints (<0.5% degradation). At system level, charge-based ACIM is close to large-scale deployment, but demands co-design strategies for quantization and retraining to compensate for analog SNR characteristics (Yoshioka et al., 2024).

7. Charge-Based ACIM Beyond Hardware: Atoms-in-Molecules and Quantum Sensing

Atoms-in-Molecules (AIM) MBIS Model

The Minimal Basis Iterative Stockholder (MBIS) technique represents another domain-specific instance of charge-based ACIM. Here, the molecular electron density is modeled as a sum of atom-centered Slater-type basis functions (pro-density), optimized via Kullback-Leibler divergence minimization against a reference ab initio density. The method iteratively refines atomic populations and orbital widths, yielding robust, transferable atomic charges for force-field development. MBIS charges display lower errors in electrostatic potential reproduction, improved interaction energies over 14 other AIM schemes, and stable performance across chemical environments. MBIS densities also adaptively scale atomic polarizabilities in the Tkatchenko–Scheffler dispersion model, achieving ∼8% RMS error in C6 coefficients (Verstraelen et al., 2016).

Charge-based AC Impedance Measurement (Quantum Sensing)

In mesoscopic physics, charge-based ACIM refers to readout techniques—such as gate-coupled radio-frequency reflectometry—where charge-dependent admittance is sensed via the amplitude and phase of RF signals reflected from a resonator-gated quantum dot. Here, the tunneling capacitance and associated susceptance modulate the resonator’s response, enabling charge sensitivity down to tens of ne$V_{\rm IN}$0 and sub-microradian phase detection. These sensors naturally integrate into scalable quantum computing architectures, eliminating the need for proximal charge sensors (Gonzalez-Zalba et al., 2014).

8. Summary and Outlook

Charge-based ACIM presents a technologically versatile paradigm for leveraging charge accumulation and redistribution for analog or hybrid computation, precise charge partitioning in chemical modeling, and sensitive charge readout in mesoscopic devices. In SRAM-based analog CIM, it stands out for its deep-submicron scalability, linearity, and ability to be hybridized with digital logic, supported by extensive benchmarking and co-design studies (Yoshioka et al., 2024). In computational chemistry, MBIS charge-based ACIM delivers accurate, robust atomic charges essential for transferable force fields and dispersion models (Verstraelen et al., 2016). In quantum sensing, charge-based ACIM attains high-fidelity, scalable readout critical for large-scale integration in quantum information systems (Gonzalez-Zalba et al., 2014). These diverse instantiations share underlying physical and mathematical principles, pointing to broad applicability and continued methodological innovation in charge-based computation and measurement.