Gain-Boosted FVF TC Stage

• Gain-boosted FVF is a transconductance stage that employs a flipped-voltage-follower topology with nested feedback loops to boost output resistance and voltage gain without extra power consumption.
• It integrates SDCM and DTMOS techniques to nearly reduce input-referred noise by 19%, ensuring superior noise performance for low-power analog front ends.
• The design achieves high closed-loop gain (>34 dB) and is ideal for ultra-low-power applications such as bioimpedance sensing in advanced CMOS implementations.

A gain-boosted flipped-voltage-follower (FVF) is a highly linear, low-noise transconductance (TC) stage topology that leverages nested local feedback loops to maximize output resistance and intrinsic gain without increasing quiescent power. In advanced low-power analog front ends, especially for applications such as bioimpedance sensing, this circuit serves as the core building block for instrumentation amplifiers that push the boundaries of noise efficiency and achievable loop gain at sub-μW power budgets (Xue et al., 3 Jan 2026).

1. Circuit Topology and Functional Overview

The gain-boosted FVF TC stage comprises a canonical flipped-voltage-follower structure with six principal MOSFET devices (M₁–M₆) and two auxiliary amplifiers: A_G (boosting the output impedance of the common-gate core) and A_R (regulating the cascode tail's output resistance). Key features include:

• M₁ (input PMOS): Operates in dynamic threshold MOS (DTMOS) configuration (bulk tied to gate), providing a composite transconductance $g_{m1} + g_{mb1}$.
• M₂ (diode-connected NMOS): Establishes bias headroom $V_L$ and part of the unity-gain feedback path.
• M₃ + R_{DE} (source-degenerated current mirror, SDCM): Realizes noise reduction via a 50 kΩ degeneration resistor, mirrored by M₃m.
• M₄ (common-gate core): Converts the source node voltage ($v_s$) to output current, with its output impedance loop-boosted by A_G.
• M₅/M₆ (cascode tail): Output resistance increased by feedback amplifier A_R.
• C_{LC} (lead compensation capacitor): Stabilizes the FVF negative feedback loop.

The critical feedback nodes are (i) the source of M₄ ($v_s$), forced by A_G to follow the input after buffering, and (ii) the drain of M₅/M₆ ($v_d$), regulated by A_R for optimal cascode operation. This dual-feedback structure sharply boosts the output resistance and hence the intrinsic voltage gain of the stage, without incurring static power increase.

2. Small-Signal Analysis and Key Equations

The small-signal behavior of the gain-boosted FVF is described by:

• Output Resistance ($r_{o,\rm eff}$): Boosted by local feedback loops around M₄ and the cascode tail:

$$r_{o,\rm eff} = \frac{r_{o4}(1+T_G)\;\times\;r_{o5}(1+T_R)}{r_{o4}(1+T_G)\;+\;r_{o5}(1+T_R)}$$

with loop gains $T_G = A_G\,g_{m4}r_{o4}$ and $T_R = A_R\,g_{m5}r_{o5}$.

• Effective Input Transconductance ($g_{m,\rm eff}$):

$V_L$0

assuming a high-gain feedback buffer around the M₁–M₂ stage, and $V_L$1 due to DTMOS action.

• Voltage Gain ($V_L$2):

$V_L$3

(assuming $V_L$4).

This configuration enables an increase in loop gain from 40 dB to 75 dB and in closed-loop output resistance from 4 MΩ to ≈120 MΩ (see Section 6).

3. Gain-Boosting Mechanisms

Two feedback loops underpin the gain-boosted FVF performance:

• Common-Gate Core Boost (M₄, via A_G): A_G senses $V_L$5 and controls M₄’s gate, increasing $V_L$6 by $V_L$7.
• Cascode Tail Boost (M₅/M₆, via A_R): A_R regulates the drain voltage, enhancing $V_L$8 by $V_L$9.

Since these impedances are parallel, the combined $v_s$0 can exceed 100 MΩ even if the intrinsic $v_s$1 of individual devices is only a few MΩ. This elevated value enables very high open-loop gain ($v_s$2) with no increase in quiescent current. The effect on loop closure allows use of low input resistance ($v_s$3), e.g., 4 kΩ, while achieving >34 dB closed-loop gain, benefiting low-noise analog front ends (Xue et al., 3 Jan 2026).

4. Noise-Reduction Techniques

To further minimize input-referred noise, two orthogonal strategies are combined:

• Source-Degenerated Current Mirror (SDCM):
  • Adding a degeneration resistor $v_s$4 (50 kΩ) to M₃ drastically lowers output noise. The effective transconductance becomes:

  $v_s$5

  for large $v_s$6. - The SDCM reduces current mirror noise by $v_s$7 ($v_s$8 decrease in this design).

• Dynamic-Threshold MOS (DTMOS):
  • By tying M₁’s bulk to gate, body transconductance $v_s$9 is added:

  $v_s$0 - Net input transistor transconductance is $v_s$1, reducing M₁’s thermal noise ($v_s$2 decrease).

Combining SDCM and DTMOS yields an overall $v_s$3 reduction in input-referred noise compared to the un-boosted FVF TC stage, reaching 29.8 nV/√Hz at 100 kHz in the benchmark design.

5. Design Equations and Trade-Off Analysis

The FVF TC stage design is governed by interdependent constraints on transconductance, impedance, headroom, noise, and current. Principal design equations include:

• Transistor Sizing/Bias (M₁):

$v_s$4

ensuring

$v_s$5

• SDCM Degeneration:

$v_s$6

with $v_s$7 retained in saturation.

• Gain-Boost Amplifiers:

$v_s$8

under the power budget.

• Bandwidth:

$v_s$9

Key trade-offs:

• Increasing $v_d$0 lowers noise but raises current and headroom demand.
• Larger $v_d$1 further reduces mirror noise but introduces extra voltage drop.
• Greater $v_d$2, $v_d$3 loop-gain boosts output impedance but increases local amplifier current.

6. Performance Comparison

The following table summarizes measured and simulated improvements for the single-ended, SDCM+DTMOS-enhanced gain-boosted FVF, benchmarked against an un-boosted FVF with the same device dimensions and quiescent power:

Metric	Un-boosted FVF	Gain-Boosted FVF (SDCM+DTMOS)
Input-ref. noise (100 kHz)	36.63 nV/√Hz	29.76 nV/√Hz (−18.7%)
DC loop gain (M₄ loop)	≈ 40 dB	75 dB
Open-loop $v_d$4	3 MΩ	3 MΩ
Closed-loop $v_d$5	4 MΩ	≈120 MΩ
$v_d$6	130 μS	130 μS
$v_d$7	520	$v_d$8 (×30)
Bandwidth	1.44 MHz	1.44 MHz
Power (TC stage)	1.25 μW	1.25 μW

This demonstrates that gain boosting multiplies output resistance—and, therefore, intrinsic voltage gain—by over $v_d$9, tightening feedback closure and enabling the use of low input resistance without compromise to bandwidth or power. Simultaneously, the combined SDCM and DTMOS approaches jointly achieve a nearly $r_{o,\rm eff}$0 reduction in input-referred noise under a static $r_{o,\rm eff}$1W budget (Xue et al., 3 Jan 2026).

7. Application Context and Integration

The gain-boosted FVF TC stage forms the basis for ultra-low-power instrumentation amplifiers in bioimpedance sensing, where noise density and energy per operation are both constrained by physiological signal levels and powering requirements. The dual-loop architecture, in concert with the SDCM and DTMOS noise-reduction methods, permits unprecedented trade-offs between low noise floors, compact dynamic range, and energy efficiency. All design parameters for the reference implementation in 28 nm CMOS—achieving $r_{o,\rm eff}$2 input-referred noise, $r_{o,\rm eff}$3 bandwidth, and $r_{o,\rm eff}$4W power—are openly sourced to ensure reproducibility and facilitate subsequent performance benchmarking in future work (Xue et al., 3 Jan 2026).