Channel-Last GAA Self-Aligned Transistors

• Channel-last GAA self-aligned transistors are devices where the semiconductor channel is deposited after gate cavity and dielectric formation, ensuring enhanced interface quality.
• They employ low-temperature ALD processes to deposit oxide semiconductors within a pre-lined cavity, preventing dielectric-induced damage and achieving strong gate control.
• This integration approach is scalable for monolithic 3D systems, delivering excellent I_on/I_off ratios, near-thermal subthreshold swing, and minimal hysteresis.

Channel-last gate-all-around self-aligned transistors are transistors in which the semiconductor channel is deposited or inserted after the gate cavity and gate dielectric are formed, the gate surrounds the channel in cross-section, and the final channel definition uses the existing structure as an alignment reference. In the reported nanosheet oxide-semiconductor realization, this concept was implemented with an atomic-layer-deposited indium tungsten oxide channel, a $10\ \mathrm{nm}$ $\mathrm{HfO_2}$ gate dielectric, and a Ni gate, at a maximum process temperature of $225^\circ\mathrm{C}$, yielding $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$, $I_\mathrm{on}/I_\mathrm{off} > 10^8$, a minimum subthreshold swing of $63.3\ \mathrm{mV/dec}$, and operation without post-deposition annealing or ozone treatment (Athena et al., 24 Dec 2025).

1. Integration rationale

The immediate motivation for channel-last gate-all-around transistors is the shift from two-dimensional scaling toward monolithic three-dimensional integration. In monolithic 3D, additional transistor tiers are built sequentially in the back-end-of-line above completed silicon devices and interconnects, so processing must obey a low thermal budget and avoid chemistries that can damage lower layers. Atomic layer deposition is attractive in this setting because it is low-temperature, conformal, and suitable for high-aspect-ratio structures, while amorphous oxide semiconductors grown by ALD are promising BEOL channel materials (Athena et al., 24 Dec 2025).

Within this integration regime, back-gated oxide transistors can perform well, but back gates are not self-aligned and have weaker electrostatic control. Practical BEOL logic and memory instead require self-aligned top-gate, dual-gate, and ultimately gate-all-around devices. The central obstacle is that conventional top-gate and GAA oxide-transistor flows are channel-first: the oxide-semiconductor channel is formed first, and the gate dielectric is then deposited directly on top of it. For ALD-grown indium-oxide-based semiconductors, that dielectric-deposition step can create defects, modify stoichiometry, and alter channel structure, often driving the device toward normally-on or fully-on behavior and degrading threshold voltage, subthreshold swing, hysteresis, and off-state behavior (Athena et al., 24 Dec 2025).

Prior recovery strategies, including post-deposition annealing and ozone or ambient treatments, can partially heal such damage but introduce additional complexity and tradeoffs. The reported work argues that these steps are fundamentally problematic for BEOL and monolithic 3D because oxygen- or nitrogen-rich anneals can damage metals, diffusion barriers, and low-$k$ dielectrics. Channel-last GAA is therefore presented as an integration-order solution rather than a post hoc repair strategy: it combines the low-defect behavior associated with back-gated, channel-last-like oxide transistors with the electrostatic superiority and scalability of a self-aligned GAA architecture, while remaining fully BEOL-compatible (Athena et al., 24 Dec 2025).

2. Architectural definition

In the reported usage, three descriptors carry distinct process and device meanings. “Channel-last” means that the semiconductor channel is deposited after the gate cavity and dielectric have already been formed. “Gate-all-around” means that the gate metal and dielectric fully surround the channel in cross-section. “Self-aligned” means that the final channel definition uses the existing structure as an alignment reference, eliminating lithographic overlay between critical features and reducing parasitic overlap capacitance (Athena et al., 24 Dec 2025).

The demonstrated geometry is a nanosheet-like structure defined through a sacrificial $\mathrm{SiO_2}$ template. After the sacrificial material is removed, the resulting cavity is conformally lined with gate dielectric and then filled with the semiconductor. TEM and EDS show that the final indium tungsten oxide channel is enclosed by $\mathrm{HfO_2}$, which is in turn enclosed by the gate metal, with no remaining Si from the sacrificial template. The authors describe the architecture as geode-inspired: the cavity acts as the geode void, the dielectric as the mineral lining, and the channel as the final infill (Athena et al., 24 Dec 2025).

This definition distinguishes channel-last self-aligned GAA from earlier or adjacent GAA geometries. Lateral InAs nanowire transistors with conformal parylene dielectrics demonstrated $\Omega$-gate and gate-all-around-like electrostatics, but they did not implement channel-last processing in the advanced-logic sense, nor a true self-aligned gate-to-source/drain process; their relevance is principally electrostatic and dielectric-process analogical rather than process-architectural (Gluschke et al., 2018).

3. Materials system and process sequence

The demonstrated channel-last GAA nanosheet transistor uses ALD-grown indium tungsten oxide with $\mathrm{HfO_2}$0 W doping as the channel, $\mathrm{HfO_2}$1 $\mathrm{HfO_2}$2 as the gate dielectric, Ni as the surrounding gate metal, and a sacrificial $\mathrm{HfO_2}$3 nanosheet to define the cavity. A local back gate is formed beneath the sacrificial nanosheet, and a metal anchor supports the nanosheet in the channel-width direction. The source/drain are not described through a distinct implanted-junction scheme; instead, the final self-aligned etch removes channel material outside the active region, leaving channel material only in the gated region and contact regions at the ends (Athena et al., 24 Dec 2025).

The fabrication flow proceeds in a specific order. Patterning is performed by electron beam lithography; a local back gate and sacrificial $\mathrm{HfO_2}$4 nanosheet are deposited and patterned; a metal anchor is patterned and deposited; the sacrificial $\mathrm{HfO_2}$5 is selectively removed by room-temperature HF vapor etching with reported selectivity $\mathrm{HfO_2}$6 over Ni, creating a nanoscopic cavity; the inner cavity walls are conformally lined by PEALD $\mathrm{HfO_2}$7 of about $\mathrm{HfO_2}$8; without breaking vacuum, PEALD indium tungsten oxide of about $\mathrm{HfO_2}$9 fills the remaining cavity; and a self-aligned dry etch removes channel material outside the active region. The process was first developed with Coventor SEMulator3D simulations and then implemented experimentally (Athena et al., 24 Dec 2025).

A key integration constraint is that both $225^\circ\mathrm{C}$0 and indium tungsten oxide are deposited in situ by PEALD at $225^\circ\mathrm{C}$1 in the same ALD chamber without vacuum break. The maximum process temperature is $225^\circ\mathrm{C}$2, and no post-deposition annealing or ozone treatment is required. This combination is central to the claim of BEOL compatibility (Athena et al., 24 Dec 2025).

The experimental demonstration is a single nanosheet-style GAA device rather than a multi-sheet stack. Electrical data are given for $225^\circ\mathrm{C}$3, $225^\circ\mathrm{C}$4, and channel thicknesses $225^\circ\mathrm{C}$5, $225^\circ\mathrm{C}$6, and $225^\circ\mathrm{C}$7. Current is normalized by the footprint width, not by the wrapped perimeter (Athena et al., 24 Dec 2025).

4. Channel-first failure mechanisms and the logic of channel-last replacement

A principal technical claim of channel-last GAA integration is that the damaging process step in oxide-semiconductor top-gate and GAA flows is not the presence of a surrounding gate per se, but the sequence in which high-$225^\circ\mathrm{C}$8 dielectric deposition occurs. In channel-first stacks, ALD of $225^\circ\mathrm{C}$9 directly onto indium-oxide-based channels is described as chemically damaging because the $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$0 bond has a higher bond dissociation energy than the $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$1 bond. The proposed consequence is oxygen scavenging from indium oxide, creating oxygen vacancies that act as donor-like defects (Athena et al., 24 Dec 2025).

These oxygen vacancies have three linked consequences in the reported analysis. First, they increase free-electron concentration, causing strong $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$2-type doping and pushing the device toward normally-on or fully-on behavior. Second, they introduce interface and defect states that degrade subthreshold behavior and electrostatic control. Third, they can trigger structural modification of the channel. In blanket-stack comparisons, channel-last stacks with $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$3 first and indium tungsten oxide second remain uniformly amorphous, whereas channel-first stacks with indium tungsten oxide first and $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$4 second show interfacial nonuniformity, polycrystalline domains in STEM and FFT, and a pronounced $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$5 peak in GIXRD (Athena et al., 24 Dec 2025).

The paper further supports this interpretation by DFT. With oxygen vacancies at areal concentration $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$6, the density of states shows finite spectral weight at the Fermi level dominated by In-$I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$7 states, donor-like levels appear near the conduction-band edge, and the band structure exhibits vacancy-related nearly dispersionless impurity bands crossing or lying at the conduction-band edge. Without oxygen vacancies, the Fermi level lies below the conduction-band minimum, the gap is clean, and there are no flat defect bands crossing $I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$8, consistent with normal turn-off capability (Athena et al., 24 Dec 2025).

The broader significance is that channel-last is presented as a replacement-channel strategy that avoids the harmful sequence entirely. The dielectric is first deposited on the empty cavity walls, and the oxide-semiconductor channel is then deposited in situ on the finished dielectric. In this sequence, the channel never experiences top-dielectric deposition (Athena et al., 24 Dec 2025).

5. Electrostatics and electrical characteristics

Operation follows standard FET electrostatics, but with stronger control than top-gate or back-gate structures because the gate wraps the full nanosheet perimeter. TCAD-calibrated electron-density maps show high electron density along the nanosheet perimeter in the on state and strong suppression of electron density throughout the nanosheet in the off state. The paper uses the standard subthreshold-swing definition

$I_\mathrm{on} > 1\ \mathrm{mA/\mu m}$9

and interprets near-thermal-limit values as evidence of a low-defect dielectric/channel interface (Athena et al., 24 Dec 2025).

For a device with $I_\mathrm{on}/I_\mathrm{off} > 10^8$0, $I_\mathrm{on}/I_\mathrm{off} > 10^8$1, and $I_\mathrm{on}/I_\mathrm{off} > 10^8$2, measured at $I_\mathrm{on}/I_\mathrm{off} > 10^8$3 and $I_\mathrm{on}/I_\mathrm{off} > 10^8$4, the reported characteristics include $I_\mathrm{on}/I_\mathrm{off} > 10^8$5, $I_\mathrm{on}/I_\mathrm{off} > 10^8$6 at $I_\mathrm{on}/I_\mathrm{off} > 10^8$7 and $I_\mathrm{on}/I_\mathrm{off} > 10^8$8, and $I_\mathrm{on}/I_\mathrm{off} > 10^8$9 by constant-current extraction. For a device with $63.3\ \mathrm{mV/dec}$0, $63.3\ \mathrm{mV/dec}$1 is reported at $63.3\ \mathrm{mV/dec}$2, $63.3\ \mathrm{mV/dec}$3; the field-effect mobility exceeds $63.3\ \mathrm{mV/dec}$4 at $63.3\ \mathrm{mV/dec}$5; the minimum subthreshold swing is $63.3\ \mathrm{mV/dec}$6; the average subthreshold swing over one decade is $63.3\ \mathrm{mV/dec}$7; and the dual-sweep hysteresis is approximately $63.3\ \mathrm{mV/dec}$8 at $63.3\ \mathrm{mV/dec}$9. For a thinner channel, $k$0, the threshold voltage becomes positive at approximately $k$1, consistent with stronger gate control as the channel thickness is reduced (Athena et al., 24 Dec 2025).

Surface and stability indicators are limited but favorable. AFM on a blanket indium tungsten oxide control film shows $k$2, and the observed hysteresis of $k$3 is presented as evidence of low trap density and a high-quality interface. At the same time, the paper does not report explicit contact resistance, DIBL, or extracted $k$4 values for the demonstrated channel-last GAA devices, and it does not provide extended reliability data such as prolonged bias-stress shifts, temperature-dependent $k$5 or $k$6, ambient-exposure stability, or BTI tests (Athena et al., 24 Dec 2025).

6. Position within the broader GAA literature

The channel-last self-aligned concept occupies a specific place within a broader GAA research landscape in which geometry, interface physics, and integration sequence have often been studied separately.

Paper	Primary focus	Relation to channel-last self-aligned GAA
(Gu et al., 2011)	Top-down III-V GAA nanowire MOSFETs	True GAA, but non-self-aligned and not channel-last
(Gu et al., 2012)	Vertically stacked III-V GAA nanowire arrays	Stacked GAA architecture, but not channel-last or self-aligned
(Zhang et al., 2022)	BEOL-compatible $k$7 GAA nanoribbon FET	Oxide GAA at low temperature, but not explicitly channel-last or self-aligned
(Karapetyan et al., 9 Jul 2025)	3D metrology of buried GAA interfaces	Structural metrology directly relevant to wrapped-interface quality
(Liu et al., 2023)	Atomistic interface states in Si GAAFETs	Physics of interface-state formation in nanosheet and nanowire GAA

Earlier top-down III-V GAA nanowire MOSFETs established the electrostatic value of complete gate enclosure and, in later work, vertically stacked nanowire arrays demonstrated the density advantage of multi-tier GAA channels. Those flows, however, are described as non-self-aligned and are not channel-last in the replacement-channel sense; they rely on released channels followed by conformal gate-stack deposition and subtractive gate definition rather than the insertion of a channel into a preformed dielectric-lined cavity [(Gu et al., 2011); (Gu et al., 2012); (Gu et al., 2012)]. A BEOL-compatible single-channel $k$8 GAA nanoribbon FET later reported near $k$9 drain current in pulsed operation, but its process likewise was neither explicitly channel-last nor self-aligned (Zhang et al., 2022).

Two additional strands of work clarify why channel-last integration is consequential even beyond oxide semiconductors. Three-dimensional multislice electron ptychography on prototype silicon nanosheet GAA transistors found that in a $\mathrm{SiO_2}$0-thick channel only about $\mathrm{SiO_2}$1 of atoms remain bulk-like, with the top and bottom wrapped interfaces showing different atomic-scale roughness profiles; the top interface had RMS roughness $\mathrm{SiO_2}$2 and correlation length $\mathrm{SiO_2}$3, whereas the bottom interface had RMS roughness $\mathrm{SiO_2}$4 and more irregular morphology with pinholes and “mouse-bites” (Karapetyan et al., 9 Jul 2025). A separate multiscale Si/SiO$\mathrm{SiO_2}$5 GAAFET study identified dangling-bond-induced, strain-induced, and dipole-induced interface states, and concluded that nanosheet geometry is preferred over aggressively scaled nanowires because interface-state effects are significantly reduced (Liu et al., 2023). Together, these results suggest that channel-last self-aligned integration is not only a patterning or parasitic-capacitance strategy; it is also an interface-preservation strategy.

7. Scalability, significance, and unresolved issues

The reported channel-last GAA oxide transistor is explicitly framed as a scalable route for BEOL transistor tiers, monolithic 3D integration, future stacked logic and memory, and possibly AOS-based 3D DRAM. The concept is also proposed as generalizable beyond amorphous oxide semiconductors to other ALD-grown channel materials, potentially including two-dimensional semiconductors, whenever dielectric deposition onto the channel is damaging. Its self-aligned character is particularly important for short-channel scaling because it reduces overlay error and overlap capacitance, while the $\mathrm{SiO_2}$6 maximum process temperature is central to sequential 3D integration (Athena et al., 24 Dec 2025).

The broader significance of the work lies in its claim that deposition order is decisive. Within this view, the longstanding discrepancy between good back-gated ALD oxide transistors and problematic top-gated or GAA oxide transistors is attributed not only to electrostatics but to integration sequence. Channel-last therefore appears as a process principle: the dielectric/channel interface quality may depend more on whether the channel ever experiences dielectric deposition than on whether the final device is planar, top-gate, or all-around gate (Athena et al., 24 Dec 2025).

Important limitations remain. The demonstrated devices use $\mathrm{SiO_2}$7, not aggressively scaled logic-node dimensions; the paper does not show full stacked-device fabrication; it does not provide large-scale variability or yield data; it does not quantify parasitic resistance and capacitance in a compact-model-ready form; and the cavity-replacement process may pose manufacturing challenges at very dense dimensions. Reliability is promising but not comprehensively established, because extended bias-stress, ambient-stability, and long-term operation data are absent (Athena et al., 24 Dec 2025).

A plausible implication is that future progress in channel-last gate-all-around self-aligned transistors will depend on simultaneously solving three coupled problems: preserving the channel against dielectric-induced damage, maintaining buried interface quality around the entire channel perimeter, and embedding the resulting structure in a manufacturing flow that retains the alignment and parasitic advantages of GAA without sacrificing BEOL compatibility. Within the reported literature, the channel-last oxide nanosheet device is notable because it addresses all three in a single process concept, even though its full scaling and manufacturing envelope remains open (Athena et al., 24 Dec 2025).