Coherent Co-Packaged Optics (CPO)

• Coherent CPO is a cutting-edge optical interconnect technology that integrates coherent transceivers with high-speed ASICs to deliver Tb/s-scale, low-latency communications.
• It leverages advanced modulation formats like QPSK and QAM with silicon photonics and DSPs to achieve high spectral efficiency and energy performance.
• High-density integration and precise packaging enable multi-wavelength optical channels with reduced insertion loss, supporting disaggregated AI and scalable data center systems.

Coherent co-packaged optics (CPO) refers to the integration of coherent optical transceivers—capable of both amplitude and phase encoding—directly alongside high-speed digital ASICs at the package or module level. By leveraging silicon photonic devices and sophisticated electronic DSP engines, coherent CPO provides Tb/s-scale, spectrally efficient, and ultra-low-latency communication, facilitating the disaggregation of memory and compute in next-generation AI and data center systems. This technology targets orders-of-magnitude improvements in bandwidth density and per-bit energy consumption compared to conventional pluggable optics, addressing interconnect bottlenecks in AI/ML scaling, high-radix switching, and petabit-class system fabrics.

1. Fundamental Principles of Coherent Co-Packaged Optics

Coherent CPO leverages both the amplitude and phase of the optical carrier by employing IQ-modulation formats such as QPSK and QAM (16-QAM, 64-QAM), often with dual-polarization multiplexing for increased spectral efficiency. At the receiver, a coherent receiver architecture based on a 90° optical hybrid mixes the incoming signal $$E_{\rm sig}(t) = A_{\rm sig}(t) e^{j(\omega_c t + \phi_{\rm sig}(t))}$$ with a local oscillator $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$, yielding in-phase and quadrature (I/Q) photocurrents. This configuration enables the recovery of both amplitude and phase, essential for high-order modulation and advanced digital impairments compensation, including chromatic dispersion and polarization mode dispersion (Moazeni, 2023).

Spectral efficiency for an $M$-ary format is given by $\eta = \frac{\log_2 M}{T_s}$ in [bit/s/Hz], and for dual polarization, $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$. Example: 16-QAM at $32\,\rm GBd$ yields $8\,\rm b/s/Hz$ spectral efficiency.

Laser phase noise (linewidth $\Delta\nu$) introduces phase variance over a given symbol duration $T_s$, as $\sigma_\phi^2 = 2\pi \Delta\nu T_s$. This requires robust digital carrier phase estimation (CPE) algorithms in the receiver DSP to keep residual phase error within operational margins.

2. High-Density Integration, Bandwidth Density, and Shoreline Scaling

A central metric for CPO is shoreline (beachfront) bandwidth density: the aggregate throughput per mm of chip edge interfacing directly with optical I/O. IBM's OTV-1 CPO modules employ a silicon-photonic die (PIC) flip-chip bonded to an ASIC, with optical I/O fanned through a molded polymer waveguide array at $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$0 pitch, greatly exceeding conventional fiber-array pitches of $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$1 (Knickerbocker et al., 2024). This enables:

• 20 fibers/mm at 50 μm pitch, versus ≈8 fibers/mm for standard pluggables.
• Effective beachfront density $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$2, where $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$3 is WDM channel count and $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$4 is pitch.
• Bandwidth density $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$5, e.g., $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$6, scaling to $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$7 at $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$8 pitch.

Insertion loss per channel is kept to $$E_{\rm LO}(t) = A_{\rm LO} e^{j(\omega_c t + \phi_{\rm LO}(t))}$$9 dB, with best channels at $M$0 dB, and crosstalk $M$1 dB at $M$2 channel spacing (Knickerbocker et al., 2024).

Vertical integration is addressed by high-density evanescent couplers, such as overlapping inverse double-taper structures enabling $M$3 insertion loss, $M$4 bandwidth, and $M$5 lateral and $M$6 vertical $M$7 alignment tolerance (Weninger et al., 2022).

3. Modulation Formats, Transceiver Architectures, and Building Blocks

High-order modulation and multiplexing are core to CPO performance. MRA-MZMs and RAMZI transmitters leveraging microring modulators (MRMs) are enabling technologies:

• Microring-assisted MZMs (MRA-MZMs) demonstrate $M$8, $M$9, and energy-per-bit $\eta = \frac{\log_2 M}{T_s}$0 for QPSK and $\eta = \frac{\log_2 M}{T_s}$1 for 16-QAM (Geravand et al., 24 Sep 2025).
• C2PO (Coherent Co-packaged Optics using offset-QAM-16) transmitters employ phase-constant amplitude modulation via RAMZI structures, enabling 400 Gb/s per $\eta = \frac{\log_2 M}{T_s}$2 at 9.65 dBm laser power, with 10–100$\eta = \frac{\log_2 M}{T_s}$3 less photonic area than conventional MZI-based QAM transmitters, and DSP-free carrier phase recovery due to the constant-envelope offset-QAM constellation (Sturm et al., 13 Jun 2025).
• QD frequency comb lasers with mode-locked architectures deliver $\eta = \frac{\log_2 M}{T_s}$4 lines at 100 GHz spacing, enabling $\eta = \frac{\log_2 M}{T_s}$5 Tb/s over a single fiber and projected $\eta = \frac{\log_2 M}{T_s}$6 Tb/s with polarization multiplexing and extended WDM (Geravand et al., 24 Sep 2025).

The integration of modulators, balanced photodiodes, advanced DSP engines (for equalization, CPE, and soft-decision FEC), and high-speed electrical drivers is achieved within $\eta = \frac{\log_2 M}{T_s}$7 mm electrical paths, minimizing signal degradation and I/O energy.

4. Packaging, Coupling, and Reliability Engineering

Co-packaged modules adopt advanced assembly approaches for thermal and mechanical stability, electrical and optical co-integration, and minimized loss:

• Polymer waveguide fans-out interface optical channels from PIC edge to standard SMF arrays via adiabatic tapers, achieving low-loss, high-reliability attachment (Knickerbocker et al., 2024).
• Thermal integrity is ensured via co-integration with thermoelectric coolers and heat spreaders to stabilize modulator resonances under adjacent ASIC power densities. Resonance shifts on silicon photonics ($\eta = \frac{\log_2 M}{T_s}$8) necessitate active feedback control for high-order WDM and dense MRM arrays.
• All OTV-1 modules passed rigorous JEDEC standards (thermal cycling, damp-heat, high/low temp storage) with channel IL shifts $\eta = \frac{\log_2 M}{T_s}$9 dB after stress (Knickerbocker et al., 2024).
• Vertical couplers facilitate multi-tier stacking within co-packaged designs, enabling substantially higher port counts via fine I/O pitch ($\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$0) and tolerance for passive assembly (Weninger et al., 2022).

Key trade-offs involve alignment (sub-$\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$1 for <20 μm pitch), crosstalk, and thermal expansion management (Knickerbocker et al., 2024).

5. Energy Efficiency, Performance Metrics, and Latency

CPO targets sub-1 pJ/bit energy budgets, enabled by:

• Short electrical link lengths across the chip/package interface, eliminating the dominant copper PCB trace losses of traditional board-level optics (Knickerbocker et al., 2024, Moazeni, 2023).
• Photonic devices (MRMs, MRA-MZMs) with $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$2 modulation energy (Geravand et al., 24 Sep 2025, Sturm et al., 13 Jun 2025).
• Shared local oscillator sources for multiple coherent channels, exploiting WDM and polarization multiplexing to maximize per-port throughput.

Performance metrics for typical CPO systems:

Metric	Near-Term Value	Next-Gen Value
Bandwidth/lane	400 Gb/s (16-QAM @32GBd)	800 Gb/s–1 Tb/s (64-QAM @64–75GBd)
Beachfront density	6× vs. pluggables (~10 Tb/s/mm target)	>10 Tb/s/mm
Energy/bit	Sub-1 pJ/bit	$\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$3 pJ/bit projected
Pre-FEC BER	$\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$4	Post-FEC $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$5
Latency	$\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$6 ns (DSP, <1 m opt)	total $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$7 ns/hop

The combination of high parallel optical port count, low insertion loss, and low electrical and optical path latency is critical to meeting synchronous AI workload requirements, such as maintaining round-trip latencies $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$8s to prevent compute starvation in distributed learning (Moazeni, 2023).

6. System-Level Implications: Disaggregated AI and Petascale Interconnects

Coherent CPO enables system architectures previously precluded by copper or intensity-modulation optics:

• Disaggregated memory and compute: Direct RDMA over coherent links, bypassing local HBM and reducing software overhead by $\eta_{\rm DP} = \frac{2\log_2 M}{T_s}$9s per transaction (Moazeni, 2023).
• High-radix circuit-switched topologies: Reconfigurable fat-tree or mesh networks with microsecond reconfiguration, each node equipped with multiple CPO ports (Moazeni, 2023).
• Scaling laws: For $32\,\rm GBd$0 accelerators and $32\,\rm GBd$1 memory pools, required port count per device $32\,\rm GBd$2 and package edge density $32\,\rm GBd$3 Tb/s/mm to yield aggregate $32\,\rm GBd$4 Tb/s per GPU.
• AI training: Fivefold improvement in throughput and elimination of inter-GPU link stalls when using CPO over copper or board-level optics (Knickerbocker et al., 2024).

A plausible implication is that CPO-based fabrics will become indispensable for memory-coherent exascale AI systems as the marginal performance benefit from transistor scaling further diminishes.

7. Outlook, Challenges, and Trade-Offs

While CPO demonstrates substantial readiness for deployment, several challenges must be addressed:

• Resonator stability and wavelength control become complex at high WDM channel counts; per-ring feedback and temperature control are essential (Geravand et al., 24 Sep 2025).
• Thermal crosstalk in densely packed modulators (MRMs, MRA-MZMs) requires isolation strategies (Geravand et al., 24 Sep 2025).
• Extending fine-pitch assembly and beachfront density to $32\,\rm GBd$5m pitch mandates alignment tolerances below standard passive assembly processes (Knickerbocker et al., 2024).
• Insertion loss of packaging (fiber coupling, vertical interconnects) must approach $32\,\rm GBd$6 dB/facet for energy budgets and system margin (Knickerbocker et al., 2024, Weninger et al., 2022).
• Advanced modulation schemes (offset-QAM, DSP-free CPE) can further reduce per-bit DSP energy and circuit complexity while preserving robustness (Sturm et al., 13 Jun 2025).

Current research trajectories include comb-driven multi-Tb/s transmitters (Geravand et al., 24 Sep 2025), further MRM/RAMZI integration (Sturm et al., 13 Jun 2025), and scaling vertical coupler density (Weninger et al., 2022), outlining a roadmap to package-scale, petabit-class coherent optical interconnects.

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References:

• (Moazeni, 2023) Next-generation Co-Packaged Optics for Future Disaggregated AI Systems
• (Knickerbocker et al., 2024) Next generation Co-Packaged Optics Technology to Train & Run Generative AI Models in Data Centers and Other Computing Applications
• (Geravand et al., 24 Sep 2025) Comb-Driven Coherent Optical Transmitter for Scalable DWDM Interconnects
• (Weninger et al., 2022) High Density Vertical Optical Interconnects for Passive Assembly
• (Sturm et al., 13 Jun 2025) C2PO: Coherent Co-packaged Optics using offset-QAM-16 for Beyond PAM-4 Optical I/O