CMOS-Compatible On-Chip RIS for mm-Wave Systems

• CMOS-compatible on-chip RIS is a mm-Wave metasurface integrated on silicon that uses VO₂ phase-change to achieve binary phase states of 0° and 180°.
• The design employs a phase-delay line architecture with standard BEOL fabrication, demonstrating low insertion loss and a 27.1 dB ON/OFF contrast at 100 GHz.
• System-level integration includes local micro-heater control and calibration techniques to mitigate mutual coupling, enabling scalable beam steering for 6G communications and imaging.

A CMOS-compatible on-chip reconfigurable intelligent surface (RIS) is a millimeter-wave (mm-Wave) metasurface structure directly integrated within a silicon-based microelectronic process, capable of dynamically manipulating incident electromagnetic fields via phase and amplitude control at each subwavelength unit cell. Leveraging standard back-end-of-line (BEOL) foundry processes, these surfaces enable highly dense, energy-efficient, and digitally addressable platforms for applications in 6G mm-Wave communication, short-range imaging, and sensing. Recent experimental demonstrations utilize phase-delay line architectures incorporating phase-change materials, ensuring both low insertion loss and full BEOL compatibility, with wafer-scale integration and scalability to large arrays (Wang et al., 26 Feb 2026, Su et al., 21 Dec 2025).

1. Unit-Cell Architecture and Principle of Operation

The fundamental building block of a CMOS-compatible on-chip RIS is a phase-delay line unit cell comprising thin-film metallization and dielectrics atop a high-resistivity silicon substrate. The canonical topology consists of:

• Top Layer: A patterned copper slot (width $w_s$, length $l_s$, thickness ~1 μm), acting as a frequency-selective aperture that couples incident W-band fields into the cell.
• SiO₂ Dielectric Spacer: Thickness $h_{SiO₂} = 15\,μm$, serving to isolate and suppress parasitic conduction into the silicon substrate and facilitate the guided-wave network.
• Delay-Line Layer: Copper microstrip ($w_d = 30\,μm$, $l_d = 400\,μm$), interrupted by a vanadium dioxide (VO₂) film (~100 nm thick) precisely patterned by lift-off lithography.
• Ground Plane: Continuous copper on high-resistivity ($\rho>1\,kΩ\cdot$cm) silicon ($h_{Si}=300\,μm$) suppresses substrate loss and supports dense two-dimensional tiling.

Within each cell, the VO₂ segment modulates the effective electrical length of the guided path. In the insulating (OFF) state, current traverses a longer, high-impedance route, whereas in the metallic (ON) state, VO₂ forms a low-impedance bridge, enabling a shorter path. This results in two quantized phase states, with a design target phase shift at the resonance frequency $f_0 \approx 100.75\,$GHz:

$Δφ = φ_{\text{ON}} - φ_{\text{OFF}} = ω_0Δτ = π$

The unit cell is modeled as a frequency-dependent surface impedance,

$Z_s(ω) = R + j\left(ωL - \frac{1}{ωC}\right),$

with the corresponding reflection coefficient

$l_s$0

where $l_s$1 is the free-space impedance. Measured reflection magnitude satisfies $l_s$2 (–1.2 dB) for both phase states (Su et al., 21 Dec 2025).

| State | |S₁₁| (Simulated, dB) | Phase (°) | $l_s$3 (°) | |---------|----------------------|-----------|----------| | OFF | –1.1 | 0 | 180 | | ON | –1.0 | 180 | – |

2. Array Design, Beam Steering, and System Performance

A prototype array comprises $l_s$4 unit cells on a $l_s$5 mm pitch, forming a $l_s$6mm aperture. Free-space illumination with a W-band horn at incidence angle $l_s$7 demonstrates beam-steering via programmed binary phase patterns. Each cell is thermally switched via micro-heaters, permitting row/column-specific biasing.

The overall array factor (AF) is written as:

$l_s$8

with $l_s$9. Steering is achieved by applying spatially progressive phase patterns across the surface. For $h_{SiO₂} = 15\,μm$0 with $h_{SiO₂} = 15\,μm$1, main-beam angle $h_{SiO₂} = 15\,μm$2.

Metric	Simulated	Measured
Main-lobe angle (°)	0	0
FWHM (°)	3.2	3.5
Side-lobe level (dB)	–12.5	–11.8
ON/OFF enhancement @0°(dB)	—	27.1

Measured results yield array gain of 14.5 dBi at broadside and a 27.1 dB ON/OFF contrast (Su et al., 21 Dec 2025). Insertion loss per unit cell is ~1.2 dB. Owing to device quantization (1-bit), side-lobe levels and angular resolution follow digital reflectarray theory.

3. Frequency Response and Calibration

The slot-line structure introduces dispersion, with phase difference $h_{SiO₂} = 15\,μm$3 maintained at 180° only within a finite bandwidth ($h_{SiO₂} = 15\,μm$4GHz ≈ 0.4%). Outside the ±200 MHz band around $h_{SiO₂} = 15\,μm$5, $h_{SiO₂} = 15\,μm$6 degrades by >20°. In wideband OFDM systems, compensation schemes include:

• Subcarrier-specific baseband pre-distortion to correct for frequency-dependent phase response.
• Calibration with swept test tones on individual RIS elements to generate corrected codebooks.
• For true wideband flattening, additional tunable LC/varactor layers are needed, though not implemented in the reported design (Wang et al., 26 Feb 2026).

4. CMOS Process Integration and Fabrication

The RIS-on-chip fabrication is strictly compliant with standard BEOL flows using only copper and SiO₂:

1. 300 μm high-resistivity Si starting wafer.
2. Blanket 200 nm Cu ground plane deposition.
3. Copper phase-delay line lithography, Cu sputter, and lift-off.
4. PECVD SiO₂ of 1.5–15 μm for isolation.
5. VO₂ thin film (100–200 nm) deposited and patterned by lift-off on designated segments.
6. Final photolithography, Cu sputtering, and patterning for slot layer.

No deep reactive ion etching (DRIE) or non-CMOS-compatible steps are involved. VO₂ is integrated as a thin layer below thermal budget constraints (<200 nm, <400°C), supporting full monolithic or flip-chip co-packaging with mm-Wave transceiver dies (Su et al., 21 Dec 2025, Wang et al., 26 Feb 2026).

5. Control, System-Level Integration, and Calibration

• Addressing: Individual cells are controlled by local micro-heater drivers activated via a low-frequency serial bus (SPI-like), enabling independent or group control of VO₂ switching.
• Packaging: The architecture supports wafer-scale integration or flip-chip assembly with redistribution-layer (RDL) interconnects for digital biasing.
• Mutual Coupling Calibration: Due to dense subwavelength tiling ($h_{SiO₂} = 15\,μm$7), mutual coupling induces non-diagonal S-matrices. Factory calibration measures the $h_{SiO₂} = 15\,μm$8 coupling matrix, leading to the effective codebook:

$h_{SiO₂} = 15\,μm$9

Calibration may be maintained by periodic pilot tones or over-the-air feedback, closing the loop via baseband DSP adjustment (Wang et al., 26 Feb 2026).

• Multi-tile Coordination: Large reflectarray apertures can be formed by networking multiple RIS-on-chip tiles, mapping global beamforming commands to local VO₂ bias states.

6. Performance Metrics, Trade-offs, and Limitations

Parameter	Value
Insertion loss	~1.2 dB/cell @ $w_d = 30\,μm$0
Reflectarray bandwidth	~0.4 GHz (Δf/$w_d = 30\,μm$1 ≈ 0.4%)
Phase quantization	1-bit ($w_d = 30\,μm$2)
Element spacing	$w_d = 30\,μm$3
Power per transition	~10 mW (pulse, VO₂ heater)
Switching speed	~100 ns (VO₂ thermally-driven)
Footprint	$w_d = 30\,μm$4

Higher phase quantization (multi-bit) is feasible via additional VO₂ segments but increases complexity and cell size. Trade-offs exist between angular resolution (smaller $w_d = 30\,μm$5 preferable), mutual coupling (exacerbated by dense tiling), and control granularity. Power consumption is dominated by transient heating pulses for VO₂, with negligible static current. Key scalability considerations include:

• Thermal cross-talk between adjacent VO₂ heaters.
• Long-term reliability of VO₂ phase cycling (>10⁶ cycles reported).
• Moving toward seamless electronic addressing without external feeds (Su et al., 21 Dec 2025).

7. Applications and Outlook

CMOS-compatible on-chip RIS solutions enable monolithic or tightly-co-packaged integration with W-band (100 GHz-class) 6G transceiver front-ends. Potential application domains include:

• Dynamic wireless environment shaping (beam-forming, reflection, spatial filtering) for 6G indoor and short-range communication systems.
• Adaptive mm-Wave imaging, sensing, and localization platforms exploiting compact, low-power metasurface arrays.
• Hybrid systems utilizing both RIS and traditional phased-array modules for combined analog and digital beam-forming.

Current research emphasizes robust system-level calibration methodologies, tile-wise coordination, enhanced phase resolution, wideband operation, and further reduction of insertion loss (Wang et al., 26 Feb 2026, Su et al., 21 Dec 2025). A plausible implication is that continued material-process innovations (thin-film VO₂, alternative phase-change materials) and advanced control architectures will underpin future scalable, CMOS-integrated RIS deployments.