100-GHz CMOS-Compatible RIS

• The paper demonstrates a monolithic RIS with a stacked slot/delay-line/VO₂ cell architecture achieving a 180° phase shift with less than 1.2 dB loss.
• It utilizes phase-delay line engineering and VO₂-based switching within a CMOS process, enabling electronically steerable arrays for precise beamforming.
• The RIS achieves a 27.1 dB ON/OFF reflection contrast and validated performance through full-wave simulations and experimental measurements, positioning it as a key 6G communication building block.

A 100-GHz CMOS-compatible reconfigurable intelligent surface (RIS) on silicon demonstrates monolithic, electronically steerable reflection at millimeter-wave (mmWave) frequencies, enabling low-loss, adaptive beamforming for 6G systems. This platform integrates phase-delay line engineering and VO₂-based phase-change switching within a foundry-compatible thin-film stack. Its principal innovations are a stacked slot/delay-line/VO₂ unit-cell architecture, loss-optimized for operation near 100 GHz, and programmable array-level phase profiles supporting micron-scale, on-die reflect-arrays. The design achieves a measured 180° phase shift with less than 1.2 dB loss and a 27.1 dB ON/OFF reflection contrast, validating the concept as a system-level building block for future on-chip wireless front-ends and adaptive metasurface controllers (Su et al., 21 Dec 2025).

1. Unit Cell Structure and Phase-Delay Principle

The RIS unit cell is architected as a vertical multilayer stack optimized for CMOS process compatibility and mmWave performance.

• Top Metal Slot: A patterned copper strip-line forms an aperture with width $w_s = 187.5$ µm and length $l_s = 562.5$ µm. This functions as a frequency-selective capacitive window at $f_0 \approx 100$ GHz.
• Phase-Delay Line Layer: Below the slot, a meandering copper trace ($l_d = 400$ µm, $w_d = 30$ µm) carries embedded VO₂. The VO₂ segment bridges two copper fingers, enabling switchable path length.
• Dielectric Stack:
  • SiO₂ Isolation: PECVD SiO₂, $h_{SiO_2} = 15$ µm, $\epsilon_r \approx 3.9$, $\tan\delta \approx 0.002$.
  • Ground Plane: Fully metallized copper over high-resistivity silicon. Ground thickness is negligible compared to $\lambda_0/10$.
  • Substrate: High-resistivity silicon, $h_{Si} = 300$ µm, $l_s = 562.5$0, $l_s = 562.5$1.

The unit cell has a square footprint, $l_s = 562.5$2 mm $l_s = 562.5$3 1.125 mm.

Phase-Control Mechanism

The phase switch exploits the insulator–metal transition of VO₂:

• OFF State (VO₂-insulating): VO₂ $l_s = 562.5$4, $l_s = 562.5$5 S/m. The absence of a conducting bridge forces current to detour, increasing the effective electrical path by $l_s = 562.5$6 µm.
• ON State (VO₂-metallic): VO₂ $l_s = 562.5$7 S/m increases conductivity, virtually shorting the delay line and minimizing path length.

The resulting phase difference at $l_s = 562.5$8 GHz is governed by

$l_s = 562.5$9

where $f_0 \approx 100$0. Substituting values yields a $f_0 \approx 100$1 shift between ON and OFF states.

Layer/Material	Parameter	Value / Property
Copper slot (top)	$f_0 \approx 100$2	187.5 µm, 562.5 µm
VO₂ (phase change)	OFF: $f_0 \approx 100$3 S/m	ON: $f_0 \approx 100$4 S/m
SiO₂ thickness, $f_0 \approx 100$5	$f_0 \approx 100$6 µm, $f_0 \approx 100$7
Substrate	$f_0 \approx 100$8 µm, $f_0 \approx 100$9

2. Scalable Array Layout and Beam Steering

A 60 × 60 element array forms an electronically steerable surface.

• Element Pitch: $l_d = 400$0 mm ($l_d = 400$1 at 100 GHz).
• Aperture: $l_d = 400$2 mm total width ($l_d = 400$3).

Phase-Gradient Programming

To steer a reflected beam to angle $l_d = 400$4 in the $l_d = 400$5–$l_d = 400$6 plane, a linear phase gradient is programmed:

$l_d = 400$7

Phase profiles $l_d = 400$8 for each element are computed and then quantized to two discrete states (1-bit): $l_d = 400$9 (VO₂ ON) and $w_d = 30$0 (VO₂ OFF).

Simulated Array Patterns

• Main Lobe: At broadside ($w_d = 30$1), array factor shows a single peak with half-power beamwidth $w_d = 30$2 (theoretical: $w_d = 30$3 rad).
• Sidelobes: First sidelobe level $w_d = 30$4 dB.
• Scanned Beams: For $w_d = 30$5, main-beam gain drops $w_d = 30$6 dB, sidelobes remain below $w_d = 30$7 dB.

3. Full-Wave Simulation and Performance Metrics

Reflection and S-Parameters

Analytical and full-wave (HFSS) simulation at $w_d = 30$8 GHz (periodic boundary conditions, Floquet ports) indicate:

• Magnitude: Both ON and OFF states have $w_d = 30$9 (reflection loss $h_{SiO_2} = 15$0 dB).
• Phase Difference: $h_{SiO_2} = 15$1 ($h_{SiO_2} = 15$2).
• Bandwidth: Across $h_{SiO_2} = 15$3 GHz, phase difference remains within $h_{SiO_2} = 15$4, and reflection above $h_{SiO_2} = 15$5 dB.

Loss and Efficiency

• Insertion Loss per Cell: $h_{SiO_2} = 15$6 dB total, with dielectric/conductor losses (SiO₂, Cu, VO₂) accounting for $h_{SiO_2} = 15$7 dB.
• Aperture Efficiency: Simulated between 55% and 60%.

Parameter	Simulated/Measured Value	Conditions
Phase shift $h_{SiO_2} = 15$8	$h_{SiO_2} = 15$9	$\epsilon_r \approx 3.9$0 GHz
Reflection mag. $\epsilon_r \approx 3.9$1	$\epsilon_r \approx 3.9$2 ($\epsilon_r \approx 3.9$3 dB)	Both VO₂ states
Insertion loss	1.2 dB	Per unit cell
ON/OFF measured contrast	27.1 dB	Rx at $\epsilon_r \approx 3.9$4

4. Fabrication Workflow and CMOS Integration

The entire process flow employs methods compatible with back-end-of-line (BEOL) CMOS manufacturing.

1. Substrate Preparation: Start with a 300 µm high-resistivity silicon wafer.
2. Ground Plane: Sputter $\epsilon_r \approx 3.9$5200 nm copper.
3. Meander Line Patterning: Photolithography and lift-off for delay lines.
4. SiO₂ Deposition: PECVD, $\epsilon_r \approx 3.9$6 µm; planarized if necessary.
5. VO₂ Definition: 100 nm VO₂ via sputtering or pulsed laser deposition (PLD), lithographically patterned as bridging element.
6. Top Layer Patterning: PECVD SiO₂ passivation (optional); photolithography/lift-off to define top copper slot layer (200 nm).

All deposition, patterning, and etch steps conform to industry-standard thin-film and photolithographic protocols.

Experimental Validation

Measurement in a mmWave (up to 110 GHz) anechoic chamber uses:

• Tx: SFH-10 horn antenna at $\epsilon_r \approx 3.9$7 cm from array (far-field).
• Rx: Scanning horn measures reflected power at $\epsilon_r \approx 3.9$8 to $\epsilon_r \approx 3.9$9.

Measured specular reflection ($\tan\delta \approx 0.002$0):

• VO₂ OFF (insulating): $\tan\delta \approx 0.002$1 dB
• VO₂ ON (metallic): $\tan\delta \approx 0.002$2 dB relative to OFF
• ON/OFF Enhancement: $\tan\delta \approx 0.002$3 dB improvement

5. Capabilities and Implications for 6G Communications

The 100-GHz CMOS-compatible RIS achieves low-loss, high-contrast ($\tan\delta \approx 0.002$4 dB) and 1-bit ($\tan\delta \approx 0.002$5) phase-shift operation. The key system-level implications for 6G platforms include:

• High-Throughput Links: Enables spatially flexible, high-gain mmWave reflect-arrays for 6G backhaul and access.
• On-Chip Integration: CMOS-compatible processing supports direct integration with RF front-ends, control FPGAs/ASICs, and digital signal processors within a monolithic Si platform.
• Fast Reconfiguration: VO₂ switching in the sub-nanosecond to nanosecond regime supports beam reprogramming at MHz rates, compatible with rapidly changing channel conditions.
• Phase Quantization Scalability: Multi-bit phase tuning (2–3 bits) is readily implemented via multiple delay lines or cascaded VO₂ segments, with area as the main constraint.

However, challenges persist in precision thermal control of VO₂, scalable uniformity over full wafers, reliability over repeated switching cycles, and robust mmWave packaging under environmental stress. Nevertheless, the demonstrated fabrication flow, electrical performance, and measurement data establish a viable route toward dense, on-chip programmable metasurfaces for next-generation 6G adaptive communications (Su et al., 21 Dec 2025).