Skybridge-3D CMOS Fabric

• The paper demonstrates that Skybridge-3D CMOS Fabric, through vertical junctionless GAA transistors and native 3D interconnects, achieves over 40× density gains and up to 10× energy efficiency improvements over conventional designs.
• Skybridge-3D CMOS Fabric is defined by its uniform vertical silicon nanowire template, enabling multiple vertically stacked devices and drastically reducing interconnect lengths by up to 10×.
• Skybridge-3D CMOS Fabric integrates intrinsic thermal management with dedicated structures like HEJs and HDPPs, lowering local transistor temperatures by over 85% to enhance reliability.

Skybridge-3D CMOS fabric is a fine-grained, vertically integrated circuit technology that implements nanoscale CMOS logic, interconnect, and thermal management around a uniform array of vertical silicon nanowires. Conceived to address fundamental scaling, connectivity, and manufacturability challenges of sub-20 nm CMOS, Skybridge and its advanced variant, Skybridge-3D-CMOS (S3DC), offer an integrated device-to-system co-architecture that redefines the transistor, routing, and thermal paradigms of three-dimensional system-on-chip design. Multiple investigations by Roy, Alam, and collaborators have demonstrated, through extensive device, fabrication, and system-level simulation, as well as experimental steps, that Skybridge achieves orders-of-magnitude gains in circuit density, energy efficiency, and routability relative to planar and layer-stacked 3D CMOS approaches (Rahman et al., 2014, Rahman et al., 2015, Li et al., 2016, Shi et al., 2016).

1. Fabric Template and Device Architecture

Skybridge relies on a uniform, high-aspect-ratio array of single-crystalline vertical silicon nanowires, typically pre-doped at ND (or NA) ≈ 10¹⁹ cm⁻³, which serve as the mechanical and electrical substrate for devices, wiring, and thermal conduits (Rahman et al., 2015, Li et al., 2016). Each nanowire pillar presents a cylindrical geometry (diameters 16–200 nm, heights up to 1.1 μm), enabling fabrication of multiple vertical gate-all-around (GAA), junctionless transistors using conformal deposition.

The standard device in the Skybridge fabric is a junctionless GAA FET, characterized by:

• Heavily doped Si channel (e.g., ND ≈ 10¹⁹ cm⁻³), with typical dimensions: nanowire diameter dNW ≈ 197 nm, effective gate length L ≈ 10–20 nm.
• Gate dielectric: HfO₂, t_ox ≈ 2 nm (ε_ox ≈ 20 ε₀).
• Gate electrode: TiN, thickness ≈ 15 nm.
• Spacer: Si₃N₄, thickness ≈ 10 nm.
• Coaxial layout: Device stack wraps around the nanowire for maximal electrostatic control.

The drain current (saturation regime) for the junctionless GAA transistor is described as:

$$I_{D,\text{sat}}(V_G) \approx \mu_\text{eff} C_\text{ox} \frac{W}{L} \frac{(V_G - V_\text{th})^2}{2}$$

with $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$ and channel cross-section $A = \pi (d_\text{NW}/2)^2$ (Rahman et al., 2015). Typical device metrics at 16 nm: $I_\text{on} \approx 27\,\mu$A, $I_\text{off} \approx 0.1$ nA, SS ≈ 78 mV/dec, and $V_\text{th} \approx 0.35$ V (Rahman et al., 2014). Simulated ON/OFF ratios exceed $10^5$ at $V_\text{th}$ ≈ 0.3 V (Rahman et al., 2015).

On a single nanowire, multiple GAA FETs can be stacked longitudinally, enabling vertical logic composition and significantly increasing device density per unit footprint (Rahman et al., 2015, Li et al., 2016).

2. Three-Dimensional Interconnect and Routing

Skybridge abandons the two-dimensional, layer-by-layer routing approach of both 2D CMOS and conventional monolithic 3D ICs. Instead, it deploys native three-dimensional wiring primitives:

• Horizontal Bridges: Tungsten (W) or Cu links that connect adjacent nanowires at arbitrary heights, replacing traditional vias (Rahman et al., 2015, Li et al., 2016).
• Coaxial Routing: Metal shells (W or Cu) concentrically deposited around nanowires, isolated by low-k dielectrics, to permit vertical and shielded signal propagation (Rahman et al., 2014, Li et al., 2016).
• Power/Ground Rails: Top and bottom metal bridge layers serve as global VDD/VSS (Shi et al., 2016).

The resistance of a bridge is $R_\text{br} = \rho_W L_\text{br} / A_\text{br}$ ($\rho_W \approx 5 \times 10^{-8}\,\Omega\cdot$m). Inter-nanowire coupling capacitance is $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$0, with effective overlap $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$1 and center-to-center spacing $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$2. The native three-dimensional topology enables drastic reductions in both average and maximum interconnect length (up to 10× shorter versus 2D CMOS), permitting much smaller wire capacitance, lower RC delay, and minimal demand for repeaters (Rahman et al., 2014, Rahman et al., 2015). Rent’s rule and system-level modeling confirm that up to 90% of Skybridge interconnects are “local”, and repeater count can shrink by two orders of magnitude (Rahman et al., 2014).

Skybridge logic gates are vertically composed: multiple GAA transistors are stacked and interconnected within (or between) nanowires using bridges and coaxial structures, yielding vertical standard cells with pin-access points distributed across several layers (typically 5–9) (Shi et al., 2016).

3. Fabrication Process and Manufacturing Pathway

The Skybridge manufacturing approach replaces most pattern-and-etch steps with a series of sequential, self-aligned material depositions on pre-patterned nanowires, significantly relaxing lithographic constraints after nanowire definition (Rahman et al., 2015, Li et al., 2016). The flow is summarized as follows:

1. Substrate Doping: Blanket doping to ND (or NA) ≈ 10¹⁹ cm⁻³—no source/drain implants required.
2. Nanowire Patterning: Defined by e-beam or DUV lithography and deep RIE; only this step requires strict alignment (tolerance ~±10–20 nm).
3. Contact Formation: Anisotropic Ti (or Ni/Ti for dual-doped wires) deposition to create source/drain contacts, with sacrificial polymer fills to localize.
4. Bridge and Interconnect Formation: CVD deposition of W/Cu for bridges and coaxial shells.
5. Planarization: SU-8 or self-planarizing resist fills for inter-nanowire spaces; etch-back to expose nanowire tops.
6. Gate Stack Formation: HfO₂ ALD gate dielectric, TiN PVD/ALD gate electrode, followed by anisotropic etch-back to localize gates.
7. Spacer/ILD Deposition: CVD Si₃N₄ spacers and low-k C-SiO₂ for dielectric isolation.
8. Final Metal and Passivation: Top global metal/clock/power layers and wafer passivation.

Crucially, after the nanowire template is defined, all subsequent device and wiring features are self-aligned to the wire geometry, permitting highly regular, fine-grained 3D structures using only established CMOS materials and processes (Rahman et al., 2015, Rahman et al., 2014). The process is agnostic to small relaxations in pitch (<2× area penalty at larger pitches) (Rahman et al., 2014).

4. Intrinsic 3D Thermal Management

Skybridge integrates dedicated thermal extraction features into the fabric to prevent localized overheating—a key problem in 3D ICs. The primary structures are:

• Thermal Pillars / Heat-Dissipating Power Pillars (HDPPs): Select nanowires are reserved or metallized for high thermal conductivity; one per (10×10) transistor array achieves effective resistance $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$3K/W (for $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$4 W/m·K, $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$5, $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$6m) (Rahman et al., 2015).
• Heat Extraction Junctions (HEJs): Thermally conductive (but electrically isolating) structures placed at transistor-level hotspots, conduct heat laterally into bridges and thence into HDPPs (Rahman et al., 2014, Li et al., 2016).
• Thermal Conduction Pathways: The cylindrical nanowires themselves contribute to vertical heat flow.

Steady-state heat flow follows Fourier’s law: $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$7. Simulations show that HEJs and HDPPs limit local transistor temperature rise by over 85% (peak $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$8 falling from >1500 K to <400 K for extreme cases) and keep device operation within reliable limits (Li et al., 2016).

5. Circuit Density, Performance, and Routability

The vertical stacking of devices and true 3D interconnects enable multi-fold gains in functional density, wirelength, and energy efficiency over 2D and other 3D ICs. Key quantitative metrics:

• Functional Density: Up to 40× (multipliers, CPUs) over 16-nm planar CMOS, exceeding even the best monolithic 3D approaches by >20× (Li et al., 2016, Rahman et al., 2014, Shi et al., 2016).
• Wirelength: Average global interconnect shrinks up to 10×, median local wirelength by 3–4× (Rahman et al., 2014, Shi et al., 2016).
• Performance per Watt: Up to 10× over planar CMOS, >3× over monolithic transistor-level 3D (Rahman et al., 2014, Li et al., 2016).
• Switching Delay: $C_\text{ox} = \epsilon_\text{ox} A / t_\text{ox}$9. Reduced $A = \pi (d_\text{NW}/2)^2$0 via vertical integration leads to lower delays for equivalent drive (Rahman et al., 2015).
• Energy per Transition: $A = \pi (d_\text{NW}/2)^2$1, with reduced $A = \pi (d_\text{NW}/2)^2$2 (shorter bridges, low-overlap) dropping $A = \pi (d_\text{NW}/2)^2$3 by 30–50% (Rahman et al., 2015).
• Routability and Congestion: Pin density per layer is cut by distributing access points vertically; S3DC circuits have up to 1.6× lower routing demand than monolithic 3D ICs, and no congestion (routing demand/resource $A = \pi (d_\text{NW}/2)^2$41) across all metal layers (Shi et al., 2016).

Summary of benchmarked results (normalized to 2D CMOS) (Shi et al., 2016):

Metric	2D CMOS	T-MI (Monolithic 3D)	S3DC (Skybridge)
Area	1×	0.48–0.50×	0.10–0.11×
Wirelength	1×	0.71–0.80×	0.20–0.31×
Total Power	1×	0.78–0.83×	0.34–0.38×
PPA	1×	2.46–2.56×	24.5–26.7×

6. Design Flow, CAD, and Comparative Analysis

Skybridge incorporates a device-to-system design flow that ties 3D process/device TCAD, SPICE-level behavioral modeling, standard cell layout/RC extraction, and commercial EDA tools (LEF/DEF, Cadence Encounter, Synopsys Primetime). Predictive technology models and extracted parasitics are used for accurate full-chip validation (Shi et al., 2016, Li et al., 2016).

Skybridge addresses several fundamental bottlenecks in alternative 3D integration methods:

• Routing Flexibility: Pin-access is spread vertically, permitting up to 6 access points per cell versus 3–4 in monolithic 3D (Shi et al., 2016).
• Alignment Tolerance: Only one lithographic nanowire array definition; all subsequent device/interconnect features self-align, reducing process variability (Rahman et al., 2015, Li et al., 2016).
• Thermal Bottlenecks: Heat is extracted at the device and circuit level, rather than post-fabrication, via distributed 3D features (Li et al., 2016, Rahman et al., 2015).
• Scalability: Similar PPA at smaller and relaxed pitches; area penalty for >16 nm pitch is modest (≤2×) (Rahman et al., 2014).

7. Impact, Limitations, and Future Directions

Skybridge and S3DC present a unified architecture in which device, circuit, interconnect, thermal, and manufacturing aspects are co-designed for vertically composed 3D-ICs. The uniform vertical nanowire template and sequential, self-aligned material deposition enable drastic scaling of CMOS circuits beyond planar or stack-by-stack approaches, yielding 30–60× logic density, 3–10× performance-per-watt, and order-of-magnitude reductions in wirelength, with experimentally verified fabrication feasibility (Rahman et al., 2014, Rahman et al., 2015, Li et al., 2016). The approach leverages only established semiconductor materials and avoids high-temperature or exotic processing.

Potential limitations not resolved in the referenced data include defect tolerance for massive 3D arrays, yield at high vertical integration, and the translation of vertical logic styles to the full spectrum of circuit architectures found in standard CMOS design flows. Further experimental scaling, integration with advanced EDA/CAD, and studies of reliability and long-term operation are plausible directions, as are extensions toward memory-logic fusion and neuromorphic fabrics.

In summary, Skybridge-3D CMOS fabric constitutes a foundational fine-grained 3D IC paradigm, centered on vertical junctionless GAA devices, native 3D interconnects, and integrated thermal management, delivered using compatible and scalable manufacturing techniques (Rahman et al., 2014, Rahman et al., 2015, Li et al., 2016, Shi et al., 2016).