From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware

Abstract: Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark. Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, $F_{\mathrm{est}}$. For MDKP and MIS, an empirical operating point near $F_{\mathrm{est}}\approx 0.1$, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction $10!/2<sup>{100}$ at $n=10$; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below $F_{\mathrm{est}}=10<sup>{-3}$. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.

• The paper benchmarks several quantum optimization techniques on real hardware, linking algorithmic circuit width, gate count, and noise-induced fidelity loss.
• It employs VQE, QAOA, and qubit-efficient methods across four NP-hard problem families, with a hardware-aware protocol assessing compilation overhead and solution quality.
• Key findings reveal that circuit compression alone does not ensure better performance, as hardware noise and resource trade-offs critically limit feasibility.

Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware

Motivation and Contributions

The paper "From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware" (2607.11637) addresses a critical evaluation gap in the field of near-term quantum optimization. While numerous studies propose new quantum algorithms for combinatorial optimization, cross-family, hardware-based comparative benchmarks remain scarce, and consequentially, the operational viability of these algorithms on state-of-the-art quantum processors is poorly understood.

The authors construct an extensive, hardware-aware benchmarking protocol implementing multiple algorithmic paradigms—variational energy minimization (VQE, CVaR-VQE), QAOA-style algorithms (standard, multi-angle, warm-start), and recent qubit-efficient encodings (PCE, QRAO)—across four representative NP-hard 0–1 combinatorial problem families (MDKP, MIS, QAP, MSP). Execution is performed on IBM Heron r1/r2 processors, employing resilience-level-2 mitigation. This protocol explicitly evaluates resource consumption, circuit compilation overhead, feasibility, and the fidelity of recovered hardware solutions. Notably, the study incorporates the first real-hardware assessment of QRAO and a multi-problem PCE hardware benchmark.

Benchmark Protocol and Methodology

Problem Families and Instance Design

Four classes of combinatorial optimization problems—multi-dimensional knapsack (MDKP), max independent set (MIS), quadratic assignment (QAP), and market share (MSP)—are selected to span structurally diverse binary optimization regimes: packing, exclusivity, dense assignment, and balancing constraints. Instances are curated to ensure that some, but not all, methods remain executable on current hardware post-compilation, providing granularity in evaluating the interplay of problem structure and quantum optimization strategy.

Algorithmic Families

• Variational energy minimization: VQE and CVaR-VQE use hardware-efficient ansätze, optimizing ground-state energy or conditional value-at-risk objectives.
• QAOA-style: Standard QAOA, multi-angle, and warm-start variants leverage problem-informed alternating operators, with classical parameter optimization.
• Qubit-efficient: PCE encodes decision variables in Pauli correlators; QRAO applies quantum random access encoding, both leveraging classical post-processing for solution recovery.

Evaluation Metrics

A broad set of hardware-facing metrics is recorded:

• Algorithm-level circuit width (logical qubits pre-transpilation)
• Post-transpilation circuit complexity (physical qubits, circuit depth, two-qubit gate count)
• Execution robustness (job success, latency, shot budgets)
• Solution quality vs. classical references (optimality gap or target deviation)
• Process fidelity proxies, estimated as $$F_{\text{est}} \approx (1 - \epsilon_{2Q})^{N_{2Q}}$$, for effective hardware noise modeling.

Crucially, algorithmic circuit width and solution quality are contextualized alongside compiled resource counts—highlighting that compression strategies may trade width for depth or total gate count.

Key Empirical Findings

MDKP: Executability and Qubit-Efficient Tradeoff

On MDKP, all methods—including qubit-efficient—produce feasible hardware solutions; circuit compressions afforded by PCE and QRAO substantially increase the range of tractable instances. However, the correlation between lower circuit width and superior hardware performance is weak. For instance, QRAO attains lower optimality gaps than PCE on 8/12 instances, but PCE is best elsewhere, and resource trade-offs are non-uniform. VQE and CVaR-VQE remain robust at moderate widths (60–130 qubits), but two-qubit gate burden rapidly becomes the limiting factor.

MIS: Noise-Induced Feasibility Cliff

The MIS benchmark exposes a sharp feasibility phase boundary: small graphs are solved optimally, but feasibility collapses abruptly beyond $\sim 32$–$64$ qubits, irrespective of method. Warm-start QAOA recovers feasibility in one larger instance (1tc.64), but otherwise all methods fail as resources surpass the architecture’s practical noise threshold.

QAP: Structural and Hardware-Intrinsic Infeasibility

QAP constitutes a worst-case scenario: dense couplings, strict assignment constraints, and an exponentially small feasible subspace ensure that neither variational nor qubit-efficient methods produce feasible hardware solutions, despite successful decoding in noiseless simulation by PCE (albeit with large gaps). This clarifies that extreme circuit width reduction cannot surmount the joint penalty of hardware noise and sparse feasible geometry in high constraint-density problems.

MSP: Compression Without Robust Recovery

Though the strongest width compression is observed for MSP (PCE/QRAO cut 48–156 variable instances to 7–11 qubits), recovered solution quality drastically degrades: hardware solutions are consistently worse than those produced by standard VQE or QAOA implementations. This underscores that extreme compression does not guarantee practical benefit; recovery sensitivity and classical post-processing pose nontrivial challenges.

Compilation, Hardware Noise, and Fidelity Modeling

The paper rigorously quantifies the divergence between algorithmic-level and backend-level circuit complexity. Post-transpilation two-qubit gate counts can increase 4.5–6.2× relative to idealized circuits, especially for dense or nonlocally-entangling instances. Under median Heron r2 calibration ($\epsilon_{2Q}=3\times 10^{-3}$), two reference points emerge: $F_{\text{est}}\approx 0.1$ at $N_{2Q}\approx 770$ (the boundary of noise-dominated execution), and $F_{\text{est}}\approx 0.01$ at $N_{2Q}\approx 1540$ (deep noise domination). QAOA-family circuits routinely exceed these counts, relegating their hardware output distributions to empirical random baseline quality; matched uniform-random controls confirm that low-fidelity QAOA runs are equivalent to best-of-budget random selection, except for rare feasibility exceptions.

Compilation-only counterfactuals (e.g., optimized routing, alternative topologies) achieve no substantive transfer of QAOA circuits into the signal-preserving regime, implying that hardware and algorithmic advances, rather than incremental circuit optimization, are required for substantial improvement on these hard problems.

Practical and Theoretical Implications

Practical Deployment

• Circuits under approximately $800$ two-qubit gates at Heron r2 error rates are most likely to yield nontrivial solutions; feasibility collapses predictably with compiled resource growth.
• Qubit-efficient methods are valuable for extending accessible instance sizes, but width minimization alone does not predict hardware performance—solution recovery, compiled depth, and robustness must be jointly considered.
• Classical state-of-the-art solvers (e.g., Gurobi, CPLEX) remain dominant for all tested instances, highlighting that the contribution of quantum benchmarks is in operational pipeline diagnosis rather than raw solution quality.

Methodological Consequences

• Simulator-only evaluations systematically overestimate algorithmic utility; backend-aware benchmarking is essential for true deployability assessment.
• Structural hardness in dense constraint or sparse-feasibility regimes (as in QAP) cannot be mitigated by compression alone. Encoding and hardware improvements must be co-designed for future progress.
• Compilation and execution should be treated as first-class metrics: algorithmic design may be attractive, but operational survival of that design post-transpilation and under real-device noise is the critical determinant of value.

Future Developments and Limitations

Hardware roadmaps pointing to increased connectivity, lower error rates, and deeper critical circuits will expand the scope of viable quantum optimization benchmarks. However, exponential scaling in compiled resource requirements for dense assignment and balancing problems suggests that even anticipated improvements may not suffice for the hardest classes without novel algorithmic solutions or fundamentally new encoding paradigms.

The current study is deliberately empirical: hyperparameter sweeps, architecture-dependent tuning, and advanced mitigation strategies are not exhaustively explored, though such mechanisms may further enhance performance. Real-world hardware heterogeneity and nonuniform circuit routing mean that device-specific effects remain a practical consideration.

Conclusion

The benchmark advances the state of empirical methodology by integrating hardware-aware diagnostics, multi-family comparisons, and explicit fidelity modeling. It persuasively demonstrates that quantum optimization performance is set by a confluence of problem structure, encoding, compilation expansion, and hardware noise, and discredits the notion that algorithmic compactness or qubit-reduction alone yields performance improvement. Going forward, evaluation protocols mirroring this study—reporting transpiled metrics, execution robustness, and solution recovery as native, not auxiliary, metrics—should constitute the community benchmark for claims regarding near-term quantum optimization capability (2607.11637).